SCIS & ISIS
SCIS & ISIS 2008
Session ID : TH-B5-2
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Design of Multiple Threshold Gate with Hysteresis for Asynchronous Circuits
*Mototsune NakahodoChikatoshi YamadaYasunori Nagata
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Abstract
Asynchronous circuits are a technique in order to solve some synchronous circuits problems such as clock skew and noise. We researched NCL circuits which is one of asynchronous circuits, and it can be synthesize only "Hysteresial Threshold Gate" which is a special gate. We have proposed Hysteresial Threshold Gate in Neuron MOS. We now propose "Multiple Threshold Gate with Hysteresis" which is general gate using of a characteristic of variable threshold value in Neuron MOS. Especially this paper show that can unify hysteresis and characteristic of variable as these pay attention to two common points. We designed Multiple Threshold Gate with Hysteresis which can be operate a function as threshold 1, 2, or 3, and simulated it with SPICE. As a result, we can synthesize Multiple Threshold Gate with Hysteresis which has 3 inputs and 2 control signals and then NCL Half Adder can be synthesized in this gate.
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© 2008 Japan Society for Fuzzy Theory and Intelligent Informatics
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