The 22th JIEP Annual Meeting
Session ID : 17A-06
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Host: Japan Institute of Electronics Packaging
Layer reducing technique of number of layers in high-speed, high density multilayer printed circuit board.
*Takahiro Yagi, jyun uetani, masataka hirokawa, Satoru Haga, Katsuyuki Takayama, Yukitaka Shirakura
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