Proceedings of JIEP Annual Meeting

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The 22th JIEP Annual Meeting

Displaying 1-50 of 129 articles from this issue

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Electromagnetic Field Measurements in Microscopic Regions Using Fiber-Optic Field Probe

Mizuki Iwanami, Takashi Harada, Tsuneo Tsukagoshi, Toshiki Shimasaki

Session ID: 17A-01
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.1.0

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The Evaluation Technology of LSI Conducted Immunity using DPI Method.

Yukiharu Akiyama, Masahiko Ide, Yoshio Yagi, Eiji Iwasaki, Toshiharu H ...

Session ID: 17A-02
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.3.0

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Susceptibility characteristics of EM coupling with digital IC

Xun Sun, Jianqing Wang

Session ID: 17A-03
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.5.0

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In this study, we investigated radiated susceptibility of a microstrip line with digital IC. We employed the circuit approach by converting the incident electric and magnetic fields into equivalent current and voltage sources, respectively. As a result, we found that the digital IC exhibits a higher susceptibility for the magnetic field coupling compared to the electric field coupling.

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Microwave measurements of anisotropic complex permittivity of dielectric laminate substrates and its application to filter design

Yoshio kobayashi, Suguru Aiba, Ze-Wang Ma

Session ID: 17A-04
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.7.0

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Dielectric laminate substrates have different values of complex permittivity in the normal and tangential directions. In this paper, accurate measurement methods of these values in the microwave range are reviewed and measured values of some dielectric laminate substrates are presented. Finally, a microstrip filter and a coplanar filter are desined by using these measured values and the measured frequency responses of these filters agree very well with the designed ones.

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Influence of thermal conductive material attachment effect for electrical characteristics of microstrip.

Yousuke Yamada, Hiroyuki Motoki, Tatsuya Kobayashi, Hideyuki Nakanishi

Session ID: 17A-05
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.9.0

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Layer reducing technique of number of layers in high-speed, high density multilayer printed circuit board.

Takahiro Yagi, jyun uetani, masataka hirokawa, Satoru Haga, Katsuyuki ...

Session ID: 17A-06
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.11.0

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Coils against for Parasitic Capacitances in LSI Package Substrate

Keitaro Yamagishi, takuma ishibashi, seiichi saito

Session ID: 17A-07
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.13.0

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In this paper, it is shown that degradation of transmission characteristics in flip-chip BGA package in consequence of parasitic capacitance nearby balls and vias can be improved by inserting coils. In the case of an analysis example for a package substrate with six layers (two build-up layers, two core layers and two build-up layers), insertion loss is under 1 dB from DC to 15 GHz. This Upper frequency is equal to Nyquist Frequency of 30 Gbps serial signal or 3 times of Nyquist Frequency of 10 Gbps serial signal.

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[title in Japanese]

[in Japanese]

Session ID: 17A-08
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.15.0

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Condition on Ground Via Position of Guard Trace for Common-mode Radiation Reduction

Tohlu Matsushima, Tetsushi Watanabe, Yoshitaka Toyota, Kengo Iokibe, R ...

Session ID: 17A-09
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.17.0

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Improvement of Radiation Efficiency by Restraining Cancellation of Electromagnetic Wave on a Miniaturized Antenna for Ubiquitous Hardwares

Kohei Takeda, Takashi Masuda, Toshihiro Itoh, Tadatomo Suga

Session ID: 17A-10
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.19.0

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Reduction method of noise emision which occur at inner layer cabity of mounting area.

Hiroyuki Motoki, Hideyuki Nakanishi, Akihiro Tanaka

Session ID: 17A-11
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.21.0

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Humidity Characteristics of Complex Permittivity for Flexible Printed Circuit Board in Microwave Band

Akihisa Tsuchiya, Hideaki Sugama, Masami Sakurai, Naomi Hidaka, Osamu ...

Session ID: 17A-12
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.23.0

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Electromagnetic Interference between Printed Circuit boards connected by Flexible Printed Circuit board

Masayuki Ota, Takashi Sakusabe, Takehiro Takahashi, Noboru Schibuya

Session ID: 17A-13
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.25.0

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A Study on Elrctric Properties of PWBs with Glass Cloth Materials

Yasushi Shimada, Etsuo Watanabe

Session ID: 17A-14
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.27.0

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An optical parallel transceiver with polymeric three dimensional waveguide

Osamu Daikuhara

Session ID: 17B-01
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.29.0

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Properties and Reliabilities of Novel Silicone-Based Film Optical Waveguide Carrying PMT-Connectors

Yoshihiro Ishikawa, Kenji Hara, Tomoyuki Iwashima, Seiichi Saito, Ayak ...

Session ID: 17B-02
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.31.0

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A novel silicone-based film optical waveguide carrying PMT-connector was fabricated. Its optical loss was so small when it was connected with a MT-fiber. It showed a good reliability under high temperature and high humidity condition.

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Self-Written Optical Funnel for Optical Interconnect by Microlens-Transfer Method

Yuji Sugiura, Hiroyuki Kubo, Osamu Mikami

Session ID: 17B-03
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.33.0

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Self-Written optical connection rod by mask transfer method using dam

Yousuke Nakanishi, Masahiro Kanda, Takuya Tokuhara, Tomonori Ogawa, Os ...

Session ID: 17B-04
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.35.0

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Optimum Structure of 90-degree Optical Path Change for OE-PWB

Masahiro Kanda, Kiminori Amano, Osamu Mikami

Session ID: 17B-05
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.37.0

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Proposal and Fabrication of New cubic VCSEL Module for High mounting flexibility

Tomonori Ogawa, Masahiro Kanda, Kenichi Goto, Osamu Mikami

Session ID: 17B-06
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.39.0

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Bi-directional optical sub assembly chip using Si microlens

Daisuke SHIMURA, Ryo Sekikawa, Masahiro Uekawa, Katsumi Aoyama, Hirono ...

Session ID: 17B-07
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.41.0

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Fabrication of on-chip optical interconnection structure by using micro plating bumps

Masao Kinoshita, Takanori Shimizu, Toshihide Ueno, Junichi Fujikata, K ...

Session ID: 17B-08
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.43.0

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Packaing stress induced deterioration mechanism of signal quality in an optical modual

Atsushi Kitamura, Ken Suzuki, Hideo Miura

Session ID: 17B-09
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.45.0

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Transmission evaluation of the optical module which used optical/electric connector

Tomoki Sekiguchi, Mitsuaki Tamura, Tomomi Moriya, Wataru Sakurai

Session ID: 17B-10
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.47.0

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Development of CWDM technology using Multi-Wavelength VCSEL and Polymer Waveguide

Hiroshi Masuda, Tei-ichi Suzuki, Yoshitsugu Wakazono, Atsushi Suzuki, ...

Session ID: 17B-11
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.49.0

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High-density and Low-cost 10-Gbps x 12ch Optical Modules for High-end Optical Interconnect Applications

Takaaki Ishikawa, Atsushi Suzuki, Yoshitsugu Wakazono, Daisuke Nagao, ...

Session ID: 17B-12
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.51.0

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Fundamental Analysis of DMD for High-speed Board and Chip Level Optical Interconnects

Yoshitsugu Wakazono, Atsushi Suzuki, Takaaki Ishikawa, Yoichi Hashimot ...

Session ID: 17B-13
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.53.0

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Making processes and their issues of through silicon via

Sei-ichi Denda

Session ID: 17C-01
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.55.0

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Electroplating Technology for Through Silicon Via Copper Filling

Akira Fukunaga, Mizuki Nagai, Nobutoshi Saito, Yuji Araki, Kenichi Aka ...

Session ID: 17C-02
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.57.0

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The Formation of High-Step-Coverage Lateral Interconnection Extending overChips

Shi-yang Ji, Takafumi Fukushima, Hisashi Kino, Tetsu Tanaka, Mitsumasa ...

Session ID: 17C-03
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.59.0

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A hetero-integrated packaging (HiP) technology was known as a promising method to fabricate metal interconnections between various functional devices and chips. However, the troublesome caused by high height differences need to be solved, such as different depth-of-fields in photolithography and low coverage of each layer on chip lateral side. In the present work, the processes of semiconductor photolithography and the formation of each layer over a large step height (100mm) was carried out. The electrical properties of fabricated lateral interconnections were measured.

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Wafer Level MEMS Package

Masanobu Saruta, Hideyuki Wada, Michikazu Tomita, Kohei Matsumaru, Tat ...

Session ID: 17C-04
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.61.0

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Proposal of Low Cost Packaging Process

Kouichi Meguro, Junji Tanaka, Masanori Onodera, Junichi Kasai

Session ID: 17C-05
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.63.0

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Regarding the cost of semiconductro package, the substrate cost holds a big ratio. Therefore, to reduce the substrate cost, we developed the packaging process with using big area substrate. At this article, to realize the packaging process, we suggest the new mold method (VDCM: Vacuum Dip Compression Molding) and the method for the warpage reduction that is hard to depend on mold resin and structure of the product.

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A highly-reliable multi-layer wafer-level Cu wiring technology with resin CMP

Katsumi Kikuchi, Kouji Soejima, Hirokazu Honda, Shintaro Yamamichi

Session ID: 17C-06
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.65.0

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Silicon-Package-Board Co-design & design methodology

[in Japanese]

Session ID: 18A-01
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.67.0

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High-Speed Method to Estimate the Switching Currents in a CMOS Output Circuit

Norimasa Oka, Kengo Iokibe, Yoshitaka Toyota, Ryuji Koga

Session ID: 18A-02
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.69.0

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Multi-rate FDTD method for the fast transient simulation of 2-D free space

Yuya Nakazono, Hideki Asai

Session ID: 18A-03
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.71.0

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A Placement Method of Devices in an Analog Block based on Learning Algorithm

Yoichi Shiraishi, Naoki Watanabe

Session ID: 18A-04
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.73.0

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An Automatic Routing Method Optimizing Total Wiring Length and Wiring Route Sharings

Yoichi Shiraishi, Takanori Sakaguchi

Session ID: 18A-05
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.75.0

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Calculation of Coupling Noise between traces in Sield Casing.

Hideo Kikuchi

Session ID: 18A-06
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.77.0

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We have studied theoretical formula to get the value of coupling noisebetween traces in shield casing using models of eqivalent circuits. Resultsof simulations matched with the theoretical results.

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[title in Japanese]

[in Japanese]

Session ID: 18A-07
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.79.0

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A study of low profile multilayer balun in LTCC substrate

Shinpei Oshima, Kouji Wada, Ryuji Murata, Yukihiro Shimakata

Session ID: 18A-08
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.81.0

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A new compact multilayer balun in LTCC substrate for 2.4GHz Wireless Systems is introduced. This balun realizes small and thin size with good performance to use new structure of a half-wavelength strip line and an additional strip line. Also we verify effectiveness of this method through designing and prototyping.

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A simple multi-scale thermal analysis technique for printed wiring board models

Hideki Mizushina, Masataka Hirokawa, Jun Kamiya, Satoru Haga, Masaru I ...

Session ID: 18A-09
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.83.0

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Evaluation of thermal conductivity of Cu thin film by a periodical heating thermoreflectance method

Syugo Miyake, Aya Miyake, Ken-ichi Ikeda, Hiroyuki Takamatsu, takashi ...

Session ID: 18A-10
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.85.0

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All kinds of electronic devices are required miniaturization and multiple functions. Exothermic heat problems occur in electronic devices which are configured with components such as integrated circuits, resistors and capacitors etc. Therefore the thermal properties of thin metal films are essential for thermal design to avoid exothermic heat problems in electric devices. In this study, the thermal conductivity measurement technique for Cu thin film has been developed using a periodical heating thermoreflectance method with high spatial resolution.

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[title in Japanese]

[in Japanese], [in Japanese], [in Japanese], [in Japanese], [in Japane ...

Session ID: 18A-11
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.87.0

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Building design rules and system verification by simulation

Toru Watanabe

Session ID: 18A-12
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.89.0

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Phase effects of current sources on conducted noise simulation with EMC macro-model LECCS of multi-power supply LSI

Kengo Iokibe, Katsumi Nakamura, Yoshitaka Toyota, Ryuji Koga, Osami Wa ...

Session ID: 18A-13
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.91.0

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Verification of the Noise-Suppression Effect of 3 Terminal Capacitor for GHz IC Power Supply Noise

Haruhiko Ueno

Session ID: 18A-14
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.93.0

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The Evaluation Technology of LSI Rdiated Immunity using Stripline Method.

Yukiharu Akiyama, Eiji Iwasaki, Toshiharu Horie, Junichi Shirai, Tomom ...

Session ID: 18A-15
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.95.0

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Study on the Switching Noise Reduction effect Using the Decoupling Capacitor with Resister

Takeshi Hakoda, Takashi Sakusabe, Takehiro Takahashi, Noboru Schibuya

Session ID: 18A-16
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.97.0

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Low Impedance Layout of By-pass Capacitors

Hidetoshi Yamamoto

Session ID: 18A-17
Published: 2008
Released on J-STAGE: October 02, 2009

DOIhttps://doi.org/10.11486/ejisso.22a.0.99.0

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