Abstract
A statistical mechanical placements theory for gate array LSI and its applications for interconnection length prediction and wireablity analysis are described. A gate array is defined as v_1×v_2 grid graph and logic circuit is done as a graph with at most one edge between a pair of verteices. In a placement we condider a wire as a particle and a wire length as a particle energy level in statistical mechanics. Then distribution of wire length k is expressed by E_k^0=W_k/(1+exp(-v+kup)(k=l, 2, …) same as FermiDirac Statistics. The approximated distribution is describe by P_k=ke^<-(k-1)/T>(1-e^<-1/T>)^2 with temperature T and then the mean R is (l+e^<-1/T>)/(1-e^<-1/T>). This theoritical distribution fits to actual wire length distribution in spite of unique parameter R(or T). A statistical optimal placement equation is deduced for the minimum average wire length. Solutions of the equation are applicable to wire length prediction and wireability analysis practically.
