THE BULLETIN OF NATIONAL INSTITUTE of TECHNOLOGY, KISARAZU COLLEGE
Online ISSN : 2188-921X
Print ISSN : 2188-9201
ISSN-L : 0285-7901
Making Process of Super-Conductive Very Small Junction Device
Kouichi ISHII
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RESEARCH REPORT / TECHNICAL REPORT FREE ACCESS

1999 Volume 32 Pages 7-10

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Abstract
This paper is a proposal of a new SIS making process. One of a proposal is a method that I easily can wire to a small junction. Another is to be a few and be able do for damage by etching to small junction. This making process is the following method. At first, it make wiring portion and large junction structure. As being next, the portion to have been shaved with etching process fill up to become a same height as another portion. Last process, it make for the very small SIS junction that was connected with for 2 series. By this method, for a flat portion, a making of a SIS junction by an electronic exposure gets possible. And, an influence of etching against SIS junction is once it. Damage by etching gets a few if it is in comparison to a former making process. Further, it thinks that this making process can apply it for a bolometer mixer device making also.
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© 1999 National Institute of Technology, Kisarazu College
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