Proceedings of JIEP Annual Meeting
The 17th JIEP Annual Meeting
Session ID : 14A-18
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Development of Stacked Packaging Using Comperssion Type Flip Chip Technology
Kazuto Nishida*Kazumichi ShimizuTakashi YuiHajime HonmaIzumi OkamotoKouji AbeTomiyo EmaHideo Koguchi
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CONFERENCE PROCEEDINGS FREE ACCESS

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Abstract

A stacked device called SEP was developed to drastically increase LSI density relative to its area on the circuit board.
The bottom-side chip was made into a flip-chip structure and attached to the substrate by the NSD method, which involves the use of stud-bumps and adhesive encapsulation film. On the top of this flip-chip LSI, another LSI was stacked and interconnected by using low-profile wire-bonding technology.
This packaging technology was able to provide a super multi-pin system LSI with more than 600 pins.
By adopting this package in a mobile communication product, the required package area on the circuit board could be reduced by 35%.

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© 2003 by The Japan Institute of Electronics Packaging
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