Abstract
To realize high-performance system, it is required to use higher data ratesand more data bits. This needs to manage the signal quality such as ISI andSSO. Since there are number of via and slits along the power and groundpath, their level can not be maintained clean. As a result, the thresholdvoltage of LSI logic is changed and the time shifts and distortion (jitter)are increased. We propose a method for analyzing simultaneous jitter of adata bus system, considering the imperfection of the power and ground path,and the effects of the non-linearity of LSIs and the random pulse response.
