On-Chip Noise Monitoring Technique and Evaluation of Power Supply Integrity in LSIs

Abstract

On-chip monitoring techniques has been applied for detailed understanding of power-supply, ground, as well as substrate noises in a practical LSI chips, in terms of noise generation as well as noise impact on circuit operation. This article introduces a compact noise monitor circuit that can be buried into digital integrated circuits. Power-supply integrity measurements demonstrated include dynamic noise inside a processor during its operation and also electromagnetic compatibility (EMC) of digital LSI chip mounted on a printed circuit board.