Proceedings of JIEP Annual Meeting

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The 23th JIEP Annual Meeting

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The 23th JIEP Annual Meeting

Design of Equalizer loaded a High Impedance Line using Genetic Algorithm

Yusuke Suzuki, Keitaro Yamagishi, Seiichi Saito, Hideyuki Oh-hashi

Session ID: 11A-01
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_1

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Design and Analysis Methodology of Electronic Devices using a Novel Electromagnetic Tool 'MomCACE'.

Masahiro Yamaoka, Kazuhide Uriu, Toru Yamada

Session ID: 11A-02
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_3

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Electromagnetic Characteristics of two PCBs connected by FPC

Masayuki Ota, Takashi Sakusabe, Takehiro Takahashi, Noboru Schibuya

Session ID: 11A-03
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_5

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Estimation of ADI-FDTD by Relaxation Method and Its Parallel Implementation

Naoki Oguni, Hideki Asai

Session ID: 11A-04
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_7

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Fast circuit simulation based on parallel - distributed LIM.

Yuta Inoue, Tadatoshi Sekine, Hideki Asai

Session ID: 11A-05
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_9

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On-Chip Noise Monitoring Technique and Evaluation of Power Supply Integrity in LSIs

Makoto Nagata

Session ID: 11A-06
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_11

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On-chip monitoring techniques has been applied for detailed understanding of power-supply, ground, as well as substrate noises in a practical LSI chips, in terms of noise generation as well as noise impact on circuit operation. This article introduces a compact noise monitor circuit that can be buried into digital integrated circuits. Power-supply integrity measurements demonstrated include dynamic noise inside a processor during its operation and also electromagnetic compatibility (EMC) of digital LSI chip mounted on a printed circuit board.

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Implovement of IBIS Model by Adding of Power-Ground Impedance under Non-Ideal Power Supply

Norimasa Oka, Kengo Iokibe, Yoshitaka Toyota, Ryuji Koga

Session ID: 11A-07
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_13

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Verification of EMI reduction by capacitor placement at embedded devices PWB

Masahiro Miura, Satoru Simada, Makoto Miyazaki, Kenji Hatsuzawa, Kimit ...

Session ID: 11A-08
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_15

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Metalizing to Cyclo Olefin Polymer Film with UV modification

Yoshiyuki Nishimura, Yosuke Iimori, Mitsuhiro Watanabe, Hideo Honma

Session ID: 11A-09
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_17

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Studies on Through-hole Filling Using PEG Derivatives

Koji Nakajima, Kentaro Nakamura, Toshiaki Matsubara, Masaharu Sugimoto ...

Session ID: 11A-10
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_19

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Investigations for influence of gold plating on attenuation in microwave transmission lines

Ryohei Yoshitomi, Yosshio Kobayashi, Zhewang Ma

Session ID: 11A-11
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_21

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Formation of Seed-Layered Plating with High Adhesion for Various Material

Genki Kanamori, Shinya Tanaka, Katsuhiko Tashiro, Mitsuhiro Watanabe, ...

Session ID: 11B-01
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_23

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Thermal mechanical properties of epoxy resins containing polyaromatic backbones

Yuichi Ohnishi, Toshiyuki Oyama, Akio Takahashi

Session ID: 11B-02
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_25

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Development of Direct Plating Process of Electroless Pd/Au on Cu

Kimiko Kudou, Yasuhiro Tanabe, Teruaki Shimoji, Hidemi Nawafune

Session ID: 11B-03
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_27

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To achieve both fine-pattern and heat-resistance, we considered the direct electroless palladium/gold plating process on copper substrate. In this results, application of newly-developed pre-coating solution enabled direct electroless palladium/gold plating on copper substrate. Compared a performance of the plating film of this process with (conventional) other surface finishing, we confirmed that this process had excellent performance, which showed the same or better performance of solderability and wire bonding ability than conventional electroless nickel/palladium/gold film.

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Development of low-temperature fabrication technique for printing metal patterns

Manabu Yoshida, Kouji Suemori, Sei Uemura, Satoshi Hoshino, Noriyuki T ...

Session ID: 11B-04
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_29

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We have developed a low-temperature process for fabricating flexible printed patterns of metals. A characteristic of our process is to utilize mechanical energies for sintering particles contained in pastes. In our process, the precise three-dimensional pressure control brings about the improvement of electrical properties in the printed patterns, the preservation of pattern accuracy and the mechanical durability of the printed patterns.

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Preparation of nano-composite passivation film by printing process at low temperature

Sei Uemura, Kouji Suemori, Manabu Yoshida, Satoshi Hoshino, Noriyuki T ...

Session ID: 11B-05
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_31

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Silicon-based Nano-composite film was prepared by wet-process at low temperature. The film was applied to electric device as a passivation film and then evaluated.

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Fabrication of Copper Damascene Patterns on Polyimide using Direct Metallization on Trench Templates generated by Imprint Lithography

Yasushi Enomoto, Yasufumi Matsumura, Kensuke Akamatsu, Hidemi Nawafune

Session ID: 11B-06
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_33

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Low-temperature Bonding of Silicon Wafers Using Metal Thin Films

Shingo Taniyama, Yinghui Wang, Tadatomo Suga

Session ID: 11B-07
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_35

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Alkaline Developable, Negative- type Photosensitive Poly(benzoxazole) Based on Poly(o-hydroxy amide), Michael Addition-type Cross-linker and Photobase Generator

Katsuhisa Mizoguchi, Mitsuru Ueda

Session ID: 11B-08
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_37

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Nowadays, photosensitive poly(benzoxazole)s (PSPBOs) are widely used as insulating materials. Year by year, the bonding wires and circuits in the micro-chips have become narrower. Therefore, it is concerned that the acids generated from photoacid generators in the PSPBO corrode the narrower copper wires and circuits via micro-chip fabrication. In this presentation, we report a novel, alkaline developable, negative-type PSPBO based on poly(o-hydroxyl amide), a micheal addition type crosslinker, photobase generator without no copper corrosion in the micro-chips.

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Requirements for the materials from jisso technologies on advanced sets

Kazunori Kato

Session ID: 11B-09
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_39

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Through the confirmation of their jisso technologies, it is discussed what kinds of characteristics and new materials are necessary for advanced sets such as cellular phone, PC, games and etc. And at the same time, the importance of standardization and DFM are explained.

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Effect of the nano-scale texture of electroplated copper thin films on their mechanical properties

Naokazu Murata, Kinji Tamakawa, Ken Suzuki, Hideo Miura

Session ID: 11B-10
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_42

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Room temperature bonding with Ag nanoparticle paste

Daisuke Wakuda, Keun-Soo Kim, Katsuaki Suganuma

Session ID: 11B-11
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_44

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Thermal Interface Material including Graphite in Vertical Formation

Rei Yamamoto, toru yoshikawa, masahiko suzuki, yuuka yoshida, tomonori ...

Session ID: 11B-12
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_46

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Package Technology of Electric devise for automotive

Akira Shintai

Session ID: 11C-01
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_48

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Hermetic Seal using Anodically-bondable LTCC Substrates

Mamoru Mori, Hideyuki Fukushi, Shuji Tanaka, Masayoshi Esashi

Session ID: 11C-02
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_50

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Creation of Functional Materials for Micro Cantilever by Electroplating

Satoshi Kaizuka, Hiroshi Wada, Yohei Wakuda, Katuhiko Tashiro, Mitsuhi ...

Session ID: 11C-03
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_52

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Improvement of Flip-chip Bonding by reduction of oxide using hydrogen radical

Tsuyoshi Nakashima, Koji Miyamoto, Mitchihiro Sato, Kanta Nogita, Akir ...

Session ID: 11C-04
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_54

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Development of fine pitch connection for a novel JISSO technique using laminating process

Kouichi Saitou, Mayumi Nakasato, Yasuyuki Yanase, Takahiro Fujii, Haji ...

Session ID: 11C-05
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_56

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Multi-scale measurement of the residual stress in semiconductor devices during their fabrication process

takuya sasaki, hideo miura

Session ID: 11C-06
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_58

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Inter Chip Fill for 3D Chip Stack

Akihiro Horibe, Fumiaki Yamada

Session ID: 11C-07
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_60

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Highly Acceleration Test on Lead-Free Solder

Masaru Morita, Nobuyuki Hayashi, Teru Nakanishi, Yasuhiro Yoneda

Session ID: 11C-08
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_62

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Chip Mounting Technology Using Low Melting Point Solder with Resin

Tomoharu Sagawa, Atsushi Kume, Yasushi Ono, Takayuki Imai

Session ID: 11C-09
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_64

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The membrane used for circuit boards in operation switches is getting smaller due to the miniaturization of digital home appliances. Accordingly, the chip mounting area must be smaller. The chip mounting technique for the membrane normally uses the encapsulation resin to increase adhesion, but it obstructs the reduction of the mounting space. To satisfy downsizing requirements, a mounting method in which encapsulation resin is not used has been developed. Low melting point solder with resin was investigated, and it could perform good mounting property and downsizing the mounting area.

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Development of Low Melting Point Sn-based Thin Film Solder for Fluxless Soldering

Eiji Sakamoto, Shohei Hata, Hisashi Aoki, Toshiaki Koizumi, Hideaki Ta ...

Session ID: 11C-10
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_66

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Selective deposition and anisotropic growth on resin using UV modification process

Tatsuyuki Joya, Yaichiro Nakamaru, Kotoku Inoue, Katsuhiko Tashiro, Hi ...

Session ID: 11C-11
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_68

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Low resistance electro conductive adhesive and the reliability

Yuuki Momokawa, tomohiro nisiyama, asao murakami, naomi ishiduka, youk ...

Session ID: 11C-12
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_70

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Miniaturization of coils for wireless power transmission and fundamental examination of secondary　voltage control for mobile electronic equipments

Naofumi Sukegawa, Hirooki Aoki, Kohji Koshiji

Session ID: 11C-13
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_72

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Test Circuit for Locating Open Leads of QFP ICS by Current Testing

Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Akira Ono, ...

Session ID: 11D-01
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_74

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Open Lead Detection of Power Supply Leads by Measuring Supply Current of Test Circuit

Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi, Masa ...

Session ID: 11D-02
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_77

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Study on minute printed wiring board inspection system with Multi-probe

Masanori Noguchi, Yukio Saito, Okitoshi Tsunoda, Tajima Takamitsu

Session ID: 11D-03
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_79

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An outward appearance inspection is used for the printed wiring board inspection but the reliability isn't enough. Because of the reliability improvement, the development of the inspection equipment that the wiring condition of the wiring can be at high speed confirmed is demanded. In this research, it developed a probe with dielectric to lose to do the turning on bad of the contact pin. It thought that the minute wiring could detect a minute flaw in doing precise positioning and taking a signal in the minute area.

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Nondestructive Failure Analysis of Au bump bonding in Flip-chip packages by Time Domain Reflectometry (TDR)

Nobuaki Shintani, Takenori Shin, Younggun Han, Woon Choi, Hajime Tomok ...

Session ID: 11D-04
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_81

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Method of detecting foreign substance in solder joint area using X-ray CT image

Kenji Noguchi, Ritsuo Asai, Takayuki Murakoshi, Atsushi Teramoto

Session ID: 11D-05
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_83

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Neural Network Visual Inspection of soldering joints with multi-angle view information

Michiya Matsushima, Naohiro Kawai, Hiroyuki Fujie, Kiyokazu Yasuda, Ko ...

Session ID: 11D-06
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_85

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Activities of Optical interconnection roadmap working group in JIP

KAZUHIKO KURATA

Session ID: 12A-01
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_87

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Coupling Characteristics of Cavity-Resonator-Integrated Grating Input/Output Coupler

Yuki Kita, Kenji Kintaka, Katsuya Shimizu, Yasuhiro Awatsuji, Syougo U ...

Session ID: 12A-02
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_90

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Embedded micromirror fabricated by using liquid immersion exposure for guided wave input/output coupling

Tomoyuki Muranishi, Katsuya Shimizu, Junichi Inoue, Kenzo Nishio, Kenj ...

Session ID: 12A-03
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_92

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Connecting between Optical Module with Self-Written Rod and Optical PWB

Tomonori Ogawa, Masahiro Kanda, Osamu Mikami, Naoyuki Kojima

Session ID: 12A-04
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_94

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Fabrication of multi channel polymer optical waveguide film by using dicing technology

Tomotsugu Kinoshita, Sho Hirano, Toshihiro Ikeshita, Koji Ishida

Session ID: 12A-05
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_96

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Reseach on Fabrication of Large Scale Flexible Optical Circuit Board without Etching Process

Naoto Kato, Toshihiro Suda, Soichi Kobayashi, Koji Ishida

Session ID: 12A-06
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_98

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Packaging Technology of MEMS Mirror Array for Wavelength Selective Switches (WSS)

mitsuo usui, shingo uchiyama, etsu hashimoto, kouichi hadama, yuuzou i ...

Session ID: 12A-07
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_100

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Requirements of packaging technologies to achieve the next generation semiconductor roadmap

Toshihiko Nishio, Hiroyuki Mori

Session ID: 12A-08
Published: 2009
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.23.0_102

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Requirements of packaging technologies to achieve the semiconductors roadmap from current 45nm gate length technology (45n) to 32n or later are estimated. When semiconductors products are categorized as Servers, Gaming, ASICs and Mobiles, the challenging items of the packaging technologies are analyzed as common tasks and the application oriented tasks from the view points of the electrical performances, the thermal performances and the reliability. In addition, a new development skim to develop those challenging tasks is proposed as an collaboration model approach.

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