High Performance Strained-SOI CMOS Technology

Abstract

We present an attractive SOI CMOS technology with a strained-Si channel for high speed ULSIs in decanano regions. The strained-SOI CMOS devices have superior characteristics, because of the combination of the SOI and the strained-Si structures. The electron and the hole mobilities are enhanced by 1.85 and 1.53, compared to those of the conventional Si MOSFETs. We demonstrate the results of high speed CMOS ring oscillators using the strained-SOI devices. We also report the device design for the strained-SOI CMOS and a new strained-SOI CMOS.