A High-Performance CMOS Bias-Offset Linear Transconductor

Abstract

A transconductor is an important building block for analog signal processing circuits. A bias-offset transconductor is known as a linear MOS transconductor. Recently, transconductors are required to have linearity, low-voltage operation, and low power consumption. This paper presents a design of a transconductor based on a bias-offset transconductor for low-power operation with high linearity. The adaptively biasing technique is used to reduce wasteful operating current without reduction of the operating range. However, using adaptively biasing technique, the linearity of transconductance characteristic is deteriorated. Two MOSFETs operating as resistors are employed to improve the linearity. Moreover, high-precision floating voltage source circuit for low-voltage low-current operation is also presented. Simulation results show that the proposed techniques are effective to realize low-power and high-linearity transconductor.