抄録
In power semiconductor devices, control of the temperature distribution of a silicon chip is very important. Temperature cycle of the chip surface causes the lift-off of the bonded wire by heat stress, which limits the lifetime of power modules. Optimized arrangement of the bonded position on the chip gives a possibility to reduce the temperature swing for a given power dissipation. In this paper, we try to apply electrothermal circuit simulation as a method of evaluating the temperature distribution on a chip and show that it can provide a method to optimize the layout of W/B point for reducing temperature gradient on a chip.
