実験値とデータシート値と近似式から構築した電力変換器の損失モデルの実機検証

抄録

This paper proposes a losses-analysis model of a DC-output converter based on the approximated equations from measurements and a datasheet. Target verification circuit consists of a DC-voltage source, a smooth capacitor, two half bridge legs, and a load inductor connected to the midpoints of the half bridge legs, which controls the continuous average DC current of the load inductor. A use of self-measured data, compared with the use of datasheet values, enables expanding the ranges of the considerable target parameters. Hence, lesser order approximated equations can deal with more target parameters with less calculation period than that in a conventional time domain simulation. In this study, calculation flow of losses from losses of power devices and an inductor to circuit losses was developed. Subsequently, a semiconductor losses model and inductor losses model were developed via the linear least square method. Finally, a 400V experimental system was developed to verify the accuracy of the circuit losses at 16 specified operating conditions by varying three verification parameters, switching frequency, gate resistance, and inductance. The result shows that the losses calculated using the proposed model has good accuracy with an error of 1.9% to 10.6% to the measured result.