Code Assignment Algorithm for Highly Parallel Multiple-Valued k-Ary Operation Circuits Using Partition Thory

抄録

Design of high-speed digital circuits such as adders and multipliers is one of the most important issues to implement high performance VLSI systems. This paper describes a code assignment algorithm for ultimately parallel multiple-valued k-ary operation circuits. Partition theory usually used in the design of sequential circuits becomes effectively employed for the fast search for code assignment problem without exhaustive procedures using logic design. We propose an efficient code assignment algorithm based on chain sets to reduce the complexity in search procedure. Experimental results and some examples are shown to demonstrate the usefulness of the algorithm.