抄録
High-speed collision detection plays an essential role in a collision warning system for highly-safe vehicles. In collision detection, high computational power is required to perform matching operation between discrete points of obstacles and a vehicle. This paper presents design of a collision detection VLSI processor using content-addressable memories (CAMs) for parallel matching operation. The VLSI processor consists of identical CAMs and processing elements (PEs) for coordinate transformation. If they are fully utilized and the fixed computation time of the VLSI processor is given as a constraint, area minimization of the VLSI processor is attributed to minimization of the area-time product of the CAM and the PE. To reduce the area-time product of the CAM, a multiport CAM (MCAM) is proposed. Each word stored in the MCAM is shared between multiple matching units so that matching operation can be performed in parallel with multiple input words without increasing memory capacity. It is shown that the area of the VLSI processor using 4-port CAMs can be reduced to 43% in comparison with the area of the VLSI processor without them under a time constraint.
