a-Si Gate Driver designs for low power AMLCD operation

Keitaro Yamashita; Toshiya Inada; Steven Deane; Paul Collins; Satoshi Kawata; Yasuyuki Onda; Masahiro Yoshiga; Jason Hector; Masahide Inoue

doi:10.11185/imt.2.1

Hardware and Devices

a-Si Gate Driver designs for low power AMLCD operation

Keitaro Yamashita, Toshiya Inada, Steven Deane, Paul Collins, Satoshi Kawata, Yasuyuki Onda, Masahiro Yoshiga, Jason Hector, Masahide Inoue

著者情報

キーワード: Amorphous silicon TFT, Gate Driver, Low Power Consumption, Partial Scanning, Shift Register, Long Lifetime

ジャーナルフリー

2007 年 2 巻 1 号 p. 1-5

DOI https://doi.org/10.11185/imt.2.1

詳細

抄録

We have developed two 1.8" QVGA (222dpi) transflective a-Si AMLCDs with integrated gate drivers. One is optimized for a very low power normal operating mode. The other can switch to an arbitrary partial scan mode. Gate driver integration results in narrow, symmetric margins, reduced cost, and fewer interconnections. Also, we minimized the number of connections to the display while retaining some to achieve very significant power reduction.

責任著者(Corresponding author)

J-STAGEへの登録はこちら（無料）