Information and Media Technologies
Online ISSN : 1881-0896
ISSN-L : 1881-0896
Hardware and Devices
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units
Zhao LeiDaisuke IkebuchiKimiyoshi UsamiMitaro NamikiMasaaki KondoHiroshi NakamuraHideharu Amano
ジャーナル フリー

2011 年 6 巻 4 号 p. 1092-1102


In this paper, we present a prototype MIPS R3000 processor, which integrates the fine-grained power gating technique into its functional units. To reduce the leakage power consumption, functional units, such as multiplier and divider can be power-gated individually according to the workload of the execution program. The prototype chip - Geyser-1 has been implemented with Fujitsu's 65nm CMOS technology; and to facilitate the design process with fine-grained power gating, a fully automated design flow has also been proposed. Comprehensive real-chip evaluations have been performed to verify the leakage reduction efficiency. According the evaluation results with benchmark programs, the fine-grained power gating can reduce the power of the processor by 5% at 25°C and 23% at 80°C.

© 2011 Information Processing Society of Japan
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