IPSJ Transactions on System and LSI Design Methodology
Online ISSN : 1882-6687
ISSN-L : 1882-6687
A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor
Ippei TanakaNaoyuki MiyagawaTomoya KimuraTakashi ImagawaHiroyuki Ochi
ジャーナル フリー

2023 年 16 巻 p. 35-44


This paper proposes a new non-volatile memory element that can be fabricated with a standard CMOS process and programmed and erased without a large current consumption. This paper also proposes a characteristics measurement circuit for the proposed memory element. Recently, self-powered sensor chips using on-chip solar cells as micro energy harvesters have been studied. For such sensor chips, however, non-volatile memory is indispensable to retain the data during nighttime. We propose a new memory element that consists of a Fishbone-in-Cage Capacitor (FiCC) and an NMOS to realize the double-gate structure of flash memory without using dedicated fabrication processes. We also develop a circuit for measuring the threshold voltage (VT) of the memory element to clarify the feasibility of using FN tunneling for programming and erasing operations to reduce the supply current. From measurement results, we show that VT shifts to 4.5V by applying a 5V programming voltage for 5sec, and the VT shift remains observable for approximately 13days. It is also seen that only a slight degradation appears after 25,000 program-erase cycles. We also investigated a non-volatile memory array architecture with bit cells, each of which consists of a pair of proposed memory elements. By writing the memory element pair complementarily, and reading with a differential amplifier, a small difference in VTs can be sensed.

© 2023 by the Information Processing Society of Japan
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