Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage

Abstract

Coverage-driven verification based on simulation has been a widely accepted methodology for verifying hardware logic designs. The goal of this methodology is to improve a metric called coverage. In this paper, we adopt toggle coverage as a target. In our prior work, we have shown an approach which combines random simulation with input pattern generation using a SAT solver. The approach has been shown to be effective throughout experiments. The run-times of the SAT-solver, however, were dominant in the verification process, which could prevent progress of verification. In order to improve the approach, we extended this prior work by parallelizing the random/SAT-based processes. Experimental results show that the parallelization can be effective for achieving higher coverage.