In this paper, we propose feature vectors for lithography hotspot detection considering the widths of wires and the distances between wires. In lithography, which is one of the semiconductor manufacturing processes, there is a pattern that is highly likely to cause an undesired short- or open-circuit, called a hotspot. Since lithography simulation used for hotspot detection requires a very long computation time, a method to more quickly detect hotspot candidates is required. In recent years, methods using machine learning have been attracting attention as those to more quickly detect hotspot candidates. In this study, to improve the accuracy of detection, we focus on the widths of wires and the distances between adjacent wires, which can be correlated with undesired open- and short-circuits, respectively. Experimental results showed that our feature vectors perform well and one of our feature vectors outperforms the others including some existing ones, in terms of F1-score and recall.

As the scale of digital circuit design increases, design and verification using conventional hardware description languages (HDLs), such as verilog-HDL and VHDL, limit efficiency. Consequently, high level synthesis (HLS), as well as domain specific languages (DSLs), which alternates conventional HDLs, are beginning to garner attention. We proposed a design framework that uses the C language as a register transfer level descriptive language. In this study, we introduced a LLVM compiler infrastructure to extend our previous work, support the C/C++ standard as the input code, and aggressively optimize the circuit design. In addition to supporting a single module generation, we extended our framework to support the hierarchical module description for efficient system design. We demonstrated the conversion of the input of C/C++ code into the verilog code, optimize its logic, and construct pipelined logic to achieve the original behavior in multiple clock cycles. Our framework offers a significantly efficient system-level hardware design and a powerful debugging environment with software development platforms and tool-sets. The generated hardware logic performs as well as or better than hand-written logic using conventional HDLs.

With the progress of the semiconductor process miniaturization, delay degradation by aging increases and threatens the reliability of the fabricated chips. The amount of the delay degradation is known to be circuit and workload dependent, but previous evaluations are based on the simulations, and the delay degradation measurement of real circuit under realistic workload has not been reported yet. The authors have already proposed a real circuit delay measurement method, which can achieve enough accuracy to measure the circuit and workload dependent delay degradation. This paper reports the measurement results utilizing the proposed method. The measured degradation is approximated by the log and the power-law functions. Methods to correct the environmental condition variation effect, and to mitigate the approximation inaccuracy caused by the random delay variation has been developed. The measurement results show large degradation amount variation, which can be attributed to the dependence on the circuits and the workloads. On the other hand, correlation of the degradation amount between different chips is rather weak. This leads to the conclusion that the temperature dependence and the random variation of the degradation amount between different transistors have large effect on the degradation amount variation.

This paper proposes a new non-volatile memory element that can be fabricated with a standard CMOS process and programmed and erased without a large current consumption. This paper also proposes a characteristics measurement circuit for the proposed memory element. Recently, self-powered sensor chips using on-chip solar cells as micro energy harvesters have been studied. For such sensor chips, however, non-volatile memory is indispensable to retain the data during nighttime. We propose a new memory element that consists of a Fishbone-in-Cage Capacitor (FiCC) and an NMOS to realize the double-gate structure of flash memory without using dedicated fabrication processes. We also develop a circuit for measuring the threshold voltage (V_T) of the memory element to clarify the feasibility of using FN tunneling for programming and erasing operations to reduce the supply current. From measurement results, we show that V_T shifts to 4.5V by applying a 5V programming voltage for 5sec, and the V_T shift remains observable for approximately 13days. It is also seen that only a slight degradation appears after 25,000 program-erase cycles. We also investigated a non-volatile memory array architecture with bit cells, each of which consists of a pair of proposed memory elements. By writing the memory element pair complementarily, and reading with a differential amplifier, a small difference in V_Ts can be sensed.

Coverage-driven verification based on simulation has been a widely accepted methodology for verifying hardware logic designs. The goal of this methodology is to improve a metric called coverage. In this paper, we adopt toggle coverage as a target. In our prior work, we have shown an approach which combines random simulation with input pattern generation using a SAT solver. The approach has been shown to be effective throughout experiments. The run-times of the SAT-solver, however, were dominant in the verification process, which could prevent progress of verification. In order to improve the approach, we extended this prior work by parallelizing the random/SAT-based processes. Experimental results show that the parallelization can be effective for achieving higher coverage.