Proposal for Non-Volatilization of Logic Cell Architecture for eFPGA IP

Abstract

As eFPGAs shift from hard IP to soft IP, this study presents the non-volatilization of PAE, a new programmable logic cell architecture replacing conventional LUTs. PAE achieves high implementation efficiency by reducing configuration memory by half while maintaining equivalent cell counts. By making PAE-based Configuration Logic Blocks (CLB) non-volatile using NVIP, the proposed eFPGA aims to achieve fast startup, low power consumption, improved reliability, and enhanced security. This approach is particularly beneficial for embedded systems and network devices with limited access post-installation. The study reports results using a 40nm MTJ/CMOS hybrid process with NVIP.