Gridless Gap Channel Routing (GGCR) is a routing problem defined in a critical routing layer in an advanced chip where a single horizontal trunk Steiner tree connects each net. The trunk widths are not unique, and trunks are allocated to partitioned routing areas, called gaps, without overlap. This paper proposes criticality-based ceiling and packing (CCAP) for GGCR to shorten the wirelength. CCAP routes a net with a smaller wirelength as much as possible by considering the congestion of gaps and the criticality of nets in terms of wirelength.

High-level synthesis (HLS) reduces design time of domain-specific accelerators from loop nests. Usually, naive usage of HLS leads to accelerators with insufficient performance, so very time-consuming manual optimizations of input programs are necessary in such cases. Scalar replacement is a promising automatic memory access optimization that removes redundant memory accesses. However, it cannot handle loops with multiple write accesses to the same array, which poses a severe limitation of its applicability. In addition, it is difficult to automatically apply scalar replacement to memory accesses with non-constant reuse distances. In this paper, we propose a novel memory access optimization technique that overcomes these existing limitations. Experimental results show that the proposed method achieves 2.14x performance gain on average with decreased total gate count of 5% for the benchmark programs which the state-of-the-art memory optimization techniques cannot optimize.

This study proposes a novel one-write eight-read (1W8R) 20T multiport static random-access memory (SRAM) for codebook quantization in deep-learning processors. We manufactured the memory using a 40nm process and achieved a memory read-access time of 2.75ns and a power consumption of 2.7pJ/byte. Furthermore, we estimated the performance of an embedded super-multiport SRAM in the pipeline of a deep-learning processor. We employed NVDLA, NVIDIA's deep learning processor, as the motif and simulated it based on the power obtained from an actual proposed memory. We estimated the power consumption when inputting a 4,094× 2,048 (4K) image into the target model, which is a U-Net semantic segmentation model. The obtained power and area reduction results were 20.24% and 26.24%, respectively.

Variable shaped-beam electron beam lithography systems are widely used for mask writing. The exposure data, which is an input for variable shaped-beam mask writing, must be a set of rectangles with considering maximum size limit. It is also crucial to fracture the layout into as few rectangles as possible for reducing the number of times the beam irradiated. Several methods have been proposed to find a solution that reduces the number of rectangles after fracturing. However, the larger the input size, the more difficult it becomes to obtain an optimal solution, and many methods give up on obtaining an optimal solution early. In this paper, we propose a new fracturing method for convex rectilinear polygons using dynamic programming, which cuts each polygon by slice-lines through concave vertices first. The proposed method can solve the problem in polynomial time. Computer experiments confirm the space and time complexity of the method and the proposed method can find the optimal solution as the existing method using ILP, but at an order of magnitude faster.

As eFPGAs shift from hard IP to soft IP, this study presents the non-volatilization of PAE, a new programmable logic cell architecture replacing conventional LUTs. PAE achieves high implementation efficiency by reducing configuration memory by half while maintaining equivalent cell counts. By making PAE-based Configuration Logic Blocks (CLB) non-volatile using NVIP, the proposed eFPGA aims to achieve fast startup, low power consumption, improved reliability, and enhanced security. This approach is particularly beneficial for embedded systems and network devices with limited access post-installation. The study reports results using a 40nm MTJ/CMOS hybrid process with NVIP.