IPSJ Transactions on System and LSI Design Methodology
Online ISSN : 1882-6687
ISSN-L : 1882-6687
A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM
Yohei UmekiKoji YanagidaShusuke YoshimotoShintaro IzumiMasahiko YoshimotoHiroshi KawaguchiKoji TsunodaToshihiro Sugii
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ジャーナル フリー

2016 年 9 巻 p. 79-83

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In this paper, in order to realize 0.4V operation of STT-MRAM, we propose the counter base read circuit. The proposed read circuit has tolerance for process variation and temperature fluctuation by changing dynamically the load curve in a time-axis at the read operation. We confirmed that the proposed read circuit can operate at the conditions of five process corners (TT, FF, FS, SF, and SS) and three temperatures (-20°C, 25°C, and 100°C) by HSPICE simulations. At the condition of TT corner and 25°C, read time of the proposed circuit is 271ns, and energy consumption is 1.05pJ at “1” read operation and 1.23pJ at “0” read operation.

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© 2016 by the Information Processing Society of Japan
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