システム制御情報学会論文誌
Online ISSN : 2185-811X
Print ISSN : 1342-5668
ISSN-L : 1342-5668
半導体製造工程におけるロット処理順序の計画方法
梅田 敏弘大村 佳也子福島 高司小西 正躬吉田 智信
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1996 年 9 巻 12 号 p. 573-581

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This paper discusses the lot scheduling method in a semiconductor fabrication, which is a typical repetitive production process. As for the algorithm to schedule lot operating sequence, simulated annealing (SA) method is applied to this scheduling formulated in the combinatorial optimization problem between machines and silicon wafer lots. To accelerate convergence of SA computation keeping up the solution quality, a new technique for reduction of the problem size and improvement of neighborhood creation are developed. Moreover, in our system, material flow in every process is simulated to consider not only the lot inventory but also the future lot arrival.

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