25-15 Image Compression Circuits for High-Speed Digital CMOS Image Sensors

Abstract

In this paper we propose image compression circuits for high-speed imaging system using a CMOS sensor. The proposed compression system consists of 4×4 2-D DCT processors and variable length coders with parallel output. DC, AC, and Zero Run Length (ZRL) components of the 2-D DCT coefficients are optimally assigned to the parallel output lines, depending on the nature of images. This method greatly simplifies the Huffman table. The compression ratio and the PSNR is comparable to JPEG.