PROCEEDINGS OF THE ITE ANNUAL CONVENTION
Online ISSN : 2424-2292
Print ISSN : 1343-1846
ISSN-L : 1343-1846
2012
Session ID : 19-5
Conference information

19-5 Low Power Consumption 12-bit Column-Parallel Two-Stage Cyclic ADC for Full-Spec SHV CMOS Image Sensor
Toshihisa WatabeKazuya KitamuraTakehide SawamotoTomohiko KosugiTomoyuki AkahoriTetsuya IidaKeigo IsobeTakashi WatanabeHiroshi ShimamotoHiroshi OhtakeSatoshi AoyamaShoji KawahitoNorifumi Egami
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Abstract
New ADC architecture which has two-stage cyclic ADC was developed for 33-Mpixel 120-fps full-spec SHV image sensor. The ADC circuit was designed in terms of reducing the power consumption, and the power consumption was 1/3 that of the conventional cyclic ADC, though the A/D conversion speed with 12-bit resolution is 1.56 times higher than that of the conventional one.
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© 2012 The Institute of Image Information and Television Engineers
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