19-5 フルスペックSHVイメージセンサ用12ビットカラム並列2段サイクリックADCの低消費電力設計(第19部門[テーマ講演]科学技術のフロンティアを切り拓くイメージセンサ技術)

抄録

New ADC architecture which has two-stage cyclic ADC was developed for 33-Mpixel 120-fps full-spec SHV image sensor. The ADC circuit was designed in terms of reducing the power consumption, and the power consumption was 1/3 that of the conventional cyclic ADC, though the A/D conversion speed with 12-bit resolution is 1.56 times higher than that of the conventional one.