Study on LSI Realization of Real-Time Extrapolative Prediction Discrete Sine Transform Coding

Abstract

2D extrapolative prediction-discrete sine transform (EP-DST) coding works efficiently with small block size (4×4) pels. This paper discusses the hardware realization of the coding, especially transfomation, with gate array. First, for hardware, reduction we introduce integer approximation of DST, named IST. The IST is realized by input-parallel and bit-serial structure with small scale hardware. 2D DST is composed by cascading the two IST's in pipeline. Second to save processing time, the computation wordlength for natural images is cut short. The disigned 2D DST transformer is composed of 2, 700 gates and is ascertained by a CAD tool to work on NTSC video signals in real time. Last. Last, we conclude coughly that, when realizing by full custom LSI, the scale and power dissipation of the EP-DST CODEC are less than 36% and 69% respectively of these of oh DCT.