Abstract
This paper describes a simple new way of quantitatively evaluating the effects of narrow channel widths and short channel lengths on DD (deep depletion) MOSFETs. Deviations from the designed channel length (ΔL) and width (ΔW) can be obtained with this method. It can also be used to quantiatively evaluate the effects of narrow channel widths on buried-channel CCDs.
In applying the technique to a variety of devices fabricated by different processes, it was discovered that ΔW in the inverted LOCOS process is 1-1.5μm shorter than that in the LOCOS process. It was also found that the effect of narrow channel widths on CCDs was strongly dependent on annealing temperature. Finally, for CCDs fabricated with the pn isolation process, it was determined that ΔW increased linearly according to the logarithm of the boron dose used in the process.