A Study of Multiple Use for Fast Processors

Abstract

This paper considers an algorithm that can realize the multiple use for plural fast processors. For this purpose, the fast switching network which connects processors and variable delays is needed. A DPS (Digital Signal Processor) chip model is assumed that includes plural multipliers, arithmetic logic units, variable delays, registers, and a cross point. The algorithm is studied for many examples and confirmed by software simulation. The digital master control system for a broadcast station is studied as an example and the DSP chip model can be very successfully used for the TV master control system Each multiplier, alu, or variable delay is very efficiently assigned and the equipment could be made much smaller.