Abstract
The gate-to-source parasitic capacitance in a-Si TFT consists of both geometric and apparent ones, in which the former is caused by the geometric overlapping between gate and source electrodes, and the latter is originated from the field overlapping due to fringe of electric field by gate and source electrodes in a-Si TFT. This presentation has given a detailed analysis on both geometric and apparent parasitic capacitances so that a contour map used to determine the storage capacitance in a-Si TFT for active matrix LCD has been drawn up. Parasitic capacitance, fringe of field, storage capacitance, thin film transistors.
