Pages 7-12
In this paper, the implemention of motion vector estimation on CMOS image sensor focal plane is described. Image contour extraction circuit is suggested for obtaining a large working rang of the bias circuit parameters with 2 OTA crossed differencial structure. Short-time digital memory is designed by Transmission Gate array, which keeps image contour information. As the kernel, a new structure of block matching, Local Parallel and Global Collumn Parallel, for high speed processing on image sensor focal plane is proposed. The processing speed is supposed to be as high as 1000 frame/s, then the serach area can be small. The block matching used in our prototype design is in a size of 2×2 pixels and a search area of ±1 pixel around the intentional block. The prototype chip including pixel and memory is designed by 1-poly 2-metal 0.7μm CMOS process.
