A feasibility study of 2GHz CMOS PLL frequency synthesizer : Development of RF circuit design technology with CAD
Details
A feasibility study of a 3rd Order type-II CMOS frequency synthesizer circuit is made with circuit simulation analysis. A 0.3um CMOS (3metal-2poly) technology is selected for the present work. The required passive elements are also fully integrated in to the circuit. The phase noise and the stability analysis are made by a C like software. As well as each building blocks in the circuit, the whole circuit is verified by SPICE Simulator also. The results show that the circuit with the area of 0.7mm2, power dissapation of 40mW@3v, phase noise of -110dBc@1MHz is attainable for the paticular case.
