A Digital CDR Circuit for PON Systems
Mitsuo Baba, Yasushi Aoki, Masaki Sato, Yasushi Wakayama, Hiroyuki Yasui, Tatuhiro Ono
Author information
Details
This paper describes a digital CDR (Clock Data Recovery) circuit for PON systems. Results of this CDR circuit have shown 0.4-U. I. p-p jitter and ±40% duty cycle distortion tolerance within 2-bit pull-in time. The circuit has been implemented on 3.3V, 0.35μm CMOS cell-based IC, and used for our PON systems of 50Mbps-156Mbps. In our evaluation, performance of this CDR with our O/E conversion circuit has met ITU-T G. 983 standard (FSAN specification).
