Abstract
This paper describes two timing nonideality issues of Digital-to-Analog Converters(DACs) ; sampling clock jitter and clock skew effects. (i)A formula for the output error power due to sampling clock jitter is derived, and this has been validated by numerical simulation ; spectrum characteristics of jitter-related noise are also examined. We have also found that when an analog lowpass filter follows the DAC and only the noise power inside the signal band is considered, increasing jitter and increasing input signal frequency degrade the DAC SNR. (ii)The clock timing skew inside the DAC causes glitch impulses. We try to characterize them by simulation and we have found the followings ; as the input frequency increases, the effects of the glitch on the DAC SNR decrease. The effects of the glitch due to upper bits on the DAC SNR and SFDR are more significant than due to lower bits. Also glitch power is mainly located at the odd-multiple frequencies of the input signal.
