ITE Technical Report
Online ISSN : 2424-1970
Print ISSN : 1342-6893
ISSN-L : 1342-6893
25.55
Showing 1-17 articles out of 17 articles from the selected issue
  • Type: Cover
    Pages Cover1-
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • Type: Index
    Pages Toc1-
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • Haruo KOBAYASHI, Naoki KUROSAWA, Ikkou MIYAUCHI, Shinya KAWAKAMI, Hide ...
    Type: Article
    Session ID: IPU2001-64
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    This paper describes two timing nonideality issues of Digital-to-Analog Converters(DACs) ; sampling clock jitter and clock skew effects. (i)A formula for the output error power due to sampling clock jitter is derived, and this has been validated by numerical simulation ; spectrum characteristics of jitter-related noise are also examined. We have also found that when an analog lowpass filter follows the DAC and only the noise power inside the signal band is considered, increasing jitter and increasing input signal frequency degrade the DAC SNR. (ii)The clock timing skew inside the DAC causes glitch impulses. We try to characterize them by simulation and we have found the followings ; as the input frequency increases, the effects of the glitch on the DAC SNR decrease. The effects of the glitch due to upper bits on the DAC SNR and SFDR are more significant than due to lower bits. Also glitch power is mainly located at the odd-multiple frequencies of the input signal.
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  • Shuichi KAWAMA, Shin'ichiro AZUMA, Kunihiko IIZUKA, Masayuki MIYA ...
    Type: Article
    Session ID: IPU2001-65
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    A combination of continuous-time and switched capacitor integrators in a simulated LC loss-less ladder yields a response with suppressed aliasing without the use of continuous-time pre-filtering. Fabricated in a 0.35-μm CMOS process, a fifth-order Cauer low-pass filter for a W-CDMA cellular phone receiver has a cut-off frequency of 1.92 MHz and aliasing suppression of better than 40 dB for 30.72-MHz sampling. Without using any tuning mechanism, a ±10-% accuracy of the cut-off frequency is achieved. As additional features the filter has variable gain from -13.3 dB to 16.4 dB and an offset compensation mechanism. With the latter, a 50-mV DC offset added to the input is suppressed to 11 mV or less at the filter output under the maximum gain setting. The filter consumes 2.81 mA at 1.8-V power supply in a die-area of 0.62 mm^2.
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  • Takaya MARUYAMA, Kazuo KANEKI, Koji TAKAHASHI, Hisayasu SATO, Tetsuya ...
    Type: Article
    Session ID: IPU2001-66
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    A single-Chip IF transceiver IC for Wideband Code Division Multiple Access systems is described. The Chip consists of two variable gain amplifiers, a quadrature modulator, a demodulator, and dual Phase Locked Loops. A new VGA for the receiver is proposed to achieve wide dynamic range. The chip draws 48 mA from 3.0V. Dynamic ranges of the VGAs for transceiver and receiver are 90 dB and 110 dB respectively.
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  • Takafumi YAMAJI, Nobuo KANOU, Tetsuro ITAKURA, Tetsuya IIDA
    Type: Article
    Session ID: IPU2001-67
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    An IF variable gain amplifier(VGA)with a quadrature demodulator(QDEM)is fabricated in a 0.25-μm CMOS technology. In order to avoid the temperature dependence of the gain control characteristic, a master-slave control technique is adopted to the exponential voltage-to-current converters using MOS transistors biased in a subthreshold exponential region. Moreover, the VGA uses both a square-law region amplifier and an exponential region amplifier to obtain the wide gain control range. The experimental results show that the prototype chip achieves an 80-dB linearly controlled gain range with 2.5 V supply voltage.
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  • Yoshiyuki SHIBAHARA, Masaru KOKUBO
    Type: Article
    Session ID: IPU2001-68
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    This paper presents evaluation results of a sub 1V Phase Locked Loop(PLL). By means of large leakage current of the deep sub-micron CMOS, the minimum oscillation frequency of a voltage controlled oscillator exceeds the desired tuning range and the PLL fails to lock. In this work, a self-calibration technique has been applied to adjust the tuning range automatically into the desired frequency band. The prototype PLL demonstrates a settling time of 10μs, a cycle-to-cycle jitter of 142ps, and a power consumption of 470μW at 0.7V-200MHz. Moreover, the maximum operating frequency of the PLL is as high as 400MHz at 0.7V.
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  • Mamoru Ugajin, Junichi Kodate, Tsuneo Tsukahara
    Type: Article
    Session ID: IPU2001-69
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    A 1-V 2-GHz receiver that exhibits an image rejection of 49 decibels is described. It consists of a low-noise amplifier, a quadrature mixer and on-chip polyphase filters, and was fabricated by 0.2-μm fully depleted CMOS/SIMOX technology. The quadrature mixer employs an LC-tuned folded structure with a common RF input for I and Q channels, and this enables 1-V operation and suppresses phase errors in LO signals. The current source of single-to-balance converter at the mixer input consists of a transistor and an LC tank in a cascode configuration. This enhances its output impedance and improves its common-mode-rejection ratio. The chip consumes 12 mW with 1-V power supply. The receiver provides an NF of 10 dB with an IIP3 of -15.7 dBm.
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  • Shinichi Yoshimura, Keiji Mabuchi, Ryoji Suzuki, Takahisa Ueno, Hirofu ...
    Type: Article
    Session ID: IPU2001-70
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    A hole accumulated diode dramatically reduces the dark current, and improves the sensitivity of longer wavelengths in a CMOS image sensor. A single correlated double sampling circuit contributes to the reduction of fixed pattern noise due to threshold voltage variations of MOS transistors. The sensor with capabilities of video rate range sensing, motion detection has also been developed. It has 192 x 124 pixels, and each pixel consists of 4 current copier cells as frame memories and a chopper comparator for signal processing. The sensor focuses on a temporal response of illumination at 48kframes/s maximum frame rate.
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  • Kimihiro Nishio, Masahiro Ohtani, Hitoshi Yamada, Akira Takasaki, Amal ...
    Type: Article
    Session ID: IPU2001-71
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    We proposed and designed simple circuits and network for detection of an approaching object based on visual systems of insects. The locusts detect the approaching object by sensing of the increase in the size and expansion velocity of the projected image on their retina. Results with the simulation program of integrated circuit emphasis(SPICE)indicated that the proposed network which is constructed with simple circuits can detect an approaching object. This network could detect the approaching velocity and the orientation of the approach. The application of the proposed network is expected to realize the detection of three-dimensional motion.
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  • Namiko IKEDA, Mamoru NAKANISHI, Koji FUJII, Takuya ADACHI, Takahiro HA ...
    Type: Article
    Session ID: IPU2001-72
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    An image enhancement algorithm is described that can be mapped with high resolution onto a compact two-dimensional array of processing elements. To prevent the structure of the object being observed from being destroyed locally, the best filter is selected and applied locally on the basis of whether or not the structure of the object is easily destroyed. Experiments showed that the proposed image enhancement has almost the same accuracy as the general method, which needs an additional processing chip. It is thus suitable for application to the compact architecture of a single-chip fingerprint-identification and CMOS vision chip that integrates a sensing circuit and a two-dimensional processing circuit.
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  • Naohisa MUKOZAKA, Haruyoshi TOYODA, Hiroshi TANAKA, Seiichiro Mizuno, ...
    Type: Article
    Session ID: IPU2001-73
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    We have designed and constructed a column parallel vision system(CPV)to realize an general purpose image processing system with a fast frame rate within 1 millisecond. The CPV system consists of an image sensor unit, a parallel processing unit and a control unit and its architecture is suitable for integration by semiconductor technology. In this paper, we focus on realizing a compact system by integrating a parallel processing unit. We show the system structure and evaluation experiment of a test chip for integration of the parallel-processing unit. In the parallel processing unit, we have applied a parallel processing LSI(128x128 PE)by using 0.35 μm CMOS technology.
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  • Tomohiro NEZUKA, Makoto IKEDA, Kunihiro ASADA
    Type: Article
    Session ID: IPU2001-74
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    A method of high speed position detection for 3-D measuremrnt using sheet light projection is presented. We can detect the position of the projected light quickly by row parallel binary-tree search using the method. We implemented the row parallel binary-tree scan effectively on a smart position sensor. The sensor has a 128×128 pixel array, row parallel controllers, a column controller, and a serial/parallel converter on a 4.9mm×4.9mm die. The sensor is designed using a 0.35μm CMOS 3-metal 2-poly-Si process. By the result of circuit simulation, the sensor can detect the position of projected light at 700Mpoints/s. The maximum speed of 3-D measurement using a 1024×1024 pixel sensor is 1kRangeMaps/s.
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  • Shoichi NAGAO, Chisato YOSHIKAWA, Takayuki HAMAMOTO, Kiyoharu AIZAWA
    Type: Article
    Session ID: IPU2001-75
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    We have been investigating the smart image sensor which has image processing circuit on the sensor. In this paper, we describe a high-speed image processing system by using binocular image compression sensors which have 128x128 pixels and FPGA, firstly. We use only 1 bit flag signals which indicate the address information of moving area for our system. By the system, tracking of moving objects and estimation of the depth can be done in real time. Next, we describe a method to detect moving area by using A/D conversion image sensor.
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  • Yusuke OIKE, Makoto IKEDA, Kunihiro ASADA
    Type: Article
    Session ID: IPU2001-76
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    In the 3-D measurement system using light projection, the sensor detects the position of the projected light on the sensor plane. The 3-D measurement system using sheet light projection can decrease frames per range map, but then the system has lower accuracy than that using spot light projection when the positions are calculated from a binary image. In this paper, we present a method of high-speed and high-accuracy position detection using row parallel processing for real-time 3-D measurement. The row parallel position detection on the sensor plane can realize high frame rate and acquire the contrast of the projected light due to searching repeatedly in one frame. By the simulation results using 0.6μm CMOS process, the frame time to acquire the position of the projected sheet light is about 17.8 μs and the sub-pixel accuracy is less than 0.1 pixel when the sensor has 256×256 pixels.
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  • Taishin Yoshida, Yasuhiro Fukunaga, Isao Takayanagi, Junichi Nakamura
    Type: Article
    Session ID: IPU2001-77
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    A new CMOS active pixel with reset noise reduction capability using capacitive feedback reset(CFR)is proposed. The CFR pixel with capacitive feedback consists of a photodiode, four MOS transistors, a feedback capacitor and a buffer capacitor. It can be fabricated in standard CMOS process, thus yielding a low noise pixel without additional process steps. It has been confirmed with a fabricated pixel structure that the reset noise is reduced to 0.39 times the reset noise level of the conventional photodiode active pixel configuration.
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  • Type: Appendix
    Pages App1-
    Published: September 07, 2001
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
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