Evaluation Results of a 0.7V-200MHz self-calibration PLL
Details
This paper presents evaluation results of a sub 1V Phase Locked Loop(PLL). By means of large leakage current of the deep sub-micron CMOS, the minimum oscillation frequency of a voltage controlled oscillator exceeds the desired tuning range and the PLL fails to lock. In this work, a self-calibration technique has been applied to adjust the tuning range automatically into the desired frequency band. The prototype PLL demonstrates a settling time of 10μs, a cycle-to-cycle jitter of 142ps, and a power consumption of 470μW at 0.7V-200MHz. Moreover, the maximum operating frequency of the PLL is as high as 400MHz at 0.7V.
