MPEG-4 Video Decoder Using VLIW Based Media Processor

Abstract

We have developed the MPEG-4 Simple Profile Video decoder using the MAPCA media processor based on the VLIW architecture. The MAPCA supports programmable video, image, and signal processing software implementation of compression and decompression algorithms, so the MAPCA matches the cost and performance features of dedicated fixed function chips, with the added flexibility to rapidly respond to evolving standards. By efficient use of SIMD instructions, the DMA engine "Data Streamer", and the VLx co-processor, the decoder can decode a video stream of CIF(352×288 pixel), 30fps and 384kbps at 50MHz of the CPU clock.