Abstract
This paper proposes the architecture of vision chip for optical flow estimation with the capability of small size, fast process and low-latency by integrating image sensor and processing circuits into a single chip. We employed the block matching algorithm (BMA) for optical flow estimation, whose search range can be reduced by increased flame rate. The DMA is carried out by the column-parallel processing circuitry, where the processing circuit at each column performs the operation for the pixels in one column. The estimated clock frequency required for the optical flow with the frame rate of 200fps is 8MHz. We also discuss the relation among the block size, brightness depth, and the accuracy with the captured images.
