Abstract
The demand for high-speed (≧30 MS/s), high-resolution (≧10 bit) and low-power operation analog-to-digital converters (ADC) is increasing because of the rapid growth in digital consumer applications (e.g., DTV and DSC) and wireless communications. Recently, the hardware in these applications has been developed with system on a chip (SoC) devices that incorporate deep sub-micron CMOS processes. Furthermore, an accurate operation at a low supply (under 1.2 V) is also required of these devices. But. it is a challenging task to design a high-accuracy and low-power ADC to operate under 1.2-V supply, because of the reduction of the input signal range. In the case of a low input signal range, the sampling capacitor value and the analog current of the op-amp used in the ADC must be increased because the thermal noise (kT/C) must be reduced to correspond with the scaling-down of the input signal power. This means that the analog power consumption and die size of the ADC increases in spite of using a low supply voltage and a deep sub-micron CMOS process. This paper describes analog design issues using a low voltage supply and a deep sub-micron process for a pipelined ADC, and introduces some new approaches on solving these problems with the pipelined ADC.
