Abstract
A 1GHz sampling and 4bit resolution flash quantizer applied to a wideband ΔΣ analog-to-digital converter was developed with a 90nm CMOS technology. In order to achieve high speed and low power consumption, a latch comparator core was design with small size MOS devices, and quantization level error was calibrated by binary capacity arrays weighted by data automatically obtained by successive approximation algorithm. By measurement of the test chip, dissipation power of 1.13mW at 600MHz and 1.0V supply operation and the maximum clock frequency of 1.5GHz were obtained. The Integral Non Linearity (INL) which was 1.24LSB before calibration was improved to 0.22LSB by the calibration.
