ITE Technical Report
Online ISSN : 2424-1970
Print ISSN : 1342-6893
ISSN-L : 1342-6893
33.39
Session ID : IST2009-82
Conference information
Delay Variation Tolerant Subthreshold Digital Circuits for Ultra-Low Power
Yuji OSAKITetsuya HIROSEKei MATSUMOTONobutaka KUROKIMasahiro NUMA
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Abstract
Subthreshold LSIs can achieve ultra-low power. However, threshold voltage variations with temperature and fabrication process have significant impact on the circuit performance. In subthreshold digital circuits, delay time changes exponentially with threshold-voltage variations. To solve this problem, we propose a delay-compensation technique for subthreshold digital circuits. On-chip threshold-voltage monitoring and supply-voltage scaling are adopted to mitigate threshold-voltage variations. As examples of subthreshold digital circuits, we have evaluated the delay time in a ring oscillator and an 8-bit ripple carry adder. With the proposed techinque, the delay time can be improved from log-normal to normal distribution.
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© 2009 The Institute of Image Information and Television Engineers
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