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Article type: Cover
Pages Cover1-
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (13K) -
Article type: Index
Pages Toc1-
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (158K) -
Koichi ISHIDA, Naoki MASUNAGA, Zhiwei ZHOU, Tadashi YASUFUKU, Tsuyoshi ...Article type: Article
Session ID: IST2009-53
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSElectromagnetic interference (EMI) that degrades the dependability of electronic devices is becoming a serious issue. To realize a measurement of EMI distribution on the surface of electronic devices, a stretchable 12×12cm^2 EMI measurement sheet was developed. This paper reports a feasibility study on the EMI measurement "furoshiki" using both a 2V Organic CMOS technology and a 0.18μm silicon CMOS.View full abstractDownload PDF (1299K) -
Daisuke FUJIMOTO, Tetsuro MATSUNO, Daisuke KOSAKA, Naoyuki HAMANISHI, ...Article type: Article
Session ID: IST2009-54
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSAn arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32×32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2×2mm^2 in a 65nm 1.2V CMOS technology. Digital noise emulation of functional logic cores such as register arrays and processing elements is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.View full abstractDownload PDF (788K) -
Yoji BANDO, Daisuke KOSAKA, Goichi YOKOMIZO, Kunihiko TSUBOI, Ying SHI ...Article type: Article
Session ID: IST2009-55
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSAn integrated power and substrate noise analysis environment targeting systems-on-chip (SoC) design was verified through comparison with on-chip noise measurements of a microprocessor chip in a 90-nm CMOS technology. The test chip includes 12 pairs of power and ground noise monitors within a processor and also embedds substrate noise evaluation areas with 120 probing points, realizing power and substrate noise measurements in terms of time-domain dynamic waveforms and spacial distribution. In addition to noise generation in digital circuits, noise propagation through on-chip silicon substrate and of chip package and board impedances needs to be carefully considered for quantitative and quality power noise simulation.View full abstractDownload PDF (1068K) -
Takushi HASHIDA, Makoto NAGATAArticle type: Article
Session ID: IST2009-56
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSChip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at 135Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by more than 30dB, purifying power supply current for internal circuits. Chip-to-chip power line communication invokes supplementary diagnosis functionality to be embedded in SoCs at the time of power connection, with the reduced cost of pin counts.View full abstractDownload PDF (720K) -
Haruya ISHIZAKI, Masayuki MIZUNOArticle type: Article
Session ID: IST2009-57
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA 27-Mbps ADC-and-FFT-less FDM receiver was developed with sensitivity of -55dBm at BER=10^<-3> and Rx power dissipation of 3mW. Furthermore, we have successfully demonstrated energy-exploitation capability from the power of unused FDM signals and interference.View full abstractDownload PDF (596K) -
Hiroaki TAKESHITA, Tomonari SAWADA, Tetsuya IIDA, Keita YASUTOMI, Shoj ...Article type: Article
Session ID: IST2009-58
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper presents a new structure and method of range calculation for CMOS time-of-flight (TOF) range image sensors using pinned photodiodes. In the proposed method, a LED light with short pulse width and small duty ratio irradiates the objects and a back-reflected light is received by the TOF range imager. In TOF range image sensors, high speed charge transfer from the light receiving part to a charge accumulator is essential. It was found that the fastest charge transfer can be realized when the lateral electric field along the axis of charge transfer is constant and this condition is met when the shape of the diode exactly follows the relationship between the fully-depleted potential and the photodiode width. A TOF range imager prototype is designed and implemented with 0.18um CMOS image sensor technology for pinned photodiode 4T pixels. In the prototype, the response of the pixel output as a function of the light pulse delay has been measured.View full abstractDownload PDF (919K) -
Zhuo LI, Hyung-June YOON, Shinya ITOH, Shoji KAWAHITOArticle type: Article
Session ID: IST2009-59
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA CMOS image sensor with two-stage charge transfer for fluorescence lifetime measurement is presented in this paper. The first transfer stage sifts fluorescence decaying in all pixels simultaneously. The second transfer stage reads out accumulated signals of each pixel sequentially at video rate. The sensor chip was fabricated using 0.18μm CMOS pinned diode image sensor process. The pixel array is 256×256. The time domain measurement uses ultraviolet laser to excite fura-2 solution which is used as fluorescent sample. The fluorescent decaying image and lifetime are successfully measured with a 250ps step time window.View full abstractDownload PDF (773K) -
Yasuhiro Oguro, Sanshiro Shishido, Toshihiko Noda, Kiyotaka Sasagawa, ...Article type: Article
Session ID: IST2009-60
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIntrinsic Optical Signal (IOS) indicates activities of brain neurons, and is one of the optical imaging methods, which records in vivo activities of cerebral cortical neurons. We designed two types of CMOS image sensor devices using 0.35-μm standard CMOS process for IOS imaging. In this paper, we describe the design details, device packaging and characterization of the sensors.View full abstractDownload PDF (1037K) -
Ayato Tagawa, Hiroki Minami, Masahiro Mitani, Toshihiko Noda, Kiyotaka ...Article type: Article
Session ID: IST2009-61
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe developed a multimodal CMOS image sensor includes an pixel array, electrodes, and LED. The electrodes were placed on the pixel array. Windows were opened in the electrode over the photodiodes to enable the fluorescence to be imaged using the pixels under the electrodes. An LED was mounted on the chip for miniaturization and the sensor chip was shaped like a shank to facilitate smooth insertion into the brain tissue. In a brain phantom, the change in the electrical potential was successfully sensed by the electrode, and green fluorescent beads were simultaneously imaged using the pixels under the electrode. We also demonstrated that the device could successfully operate in deep brain of an anesthetized mouse.View full abstractDownload PDF (1105K) -
Kazuo NakazatoArticle type: Article
Session ID: IST2009-62
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSNew high-density and low-power CMOS analog integrated circuits, CMOS source-drain follower and CMOS source-measure unit, have been developed for monolithically integrated biosensor array. These circuits do not disturb measured environment, can be fabricated by standard CMOS fabrication process, can be operated in subthreshold region, consist of 10 transistors for each basic circuit, and have good accuracy and weak dependence of temperature and device parameters. Several applications of integrated biosensor array have been investigated; pH detection, DNA detection, and bio-imagesensor utilizing photosynthesis protein complex, photosystem I, integrated with CMOS sensor circuits.View full abstractDownload PDF (1152K) -
Makoto ISHIDA, Takeshi KAWANO, Kazuaki SAWADAArticle type: Article
Session ID: IST2009-63
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSNew sensor chips with sensor array and LSI on chips which are called as smart micro sensor chips, are introduced such as Integrations of silicon micro/nano-probes and microtubes for neural interface and pH imaging sensor chips, which enable to detect impossible measurement subjects and develop new application fields.View full abstractDownload PDF (2160K) -
Masayoshi ESASHIArticle type: Article
Session ID: IST2009-64
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIntegrated MEMS have been effectively applied for capacitive sensors by integrating capacitance detection circuits and for arrayed MEMS to reduce the lead wires. Integrated MEMS are expected for RF to reduce stray inductance. Mechanical sensors for pressure, acceleration and force, biomedical devices as active catheter and ultrasound transducers and wireless chips which have multiple band MEMS filters are described as examples of the integrated MEMS.View full abstractDownload PDF (1875K) -
Kohji MITSUBAYASHIArticle type: Article
Session ID: IST2009-65
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSSeveral kinds of wearable chemical sensors were constructed by micro-fabrication techniques for measuring biochemical substances. The wearable oxygen sensor was successfully used to monitor the transcutaneous oxygen pressure by applying the device onto the forearm skin surface. Tear fluid conductivity was possible to be measured by applying the wearable sensor to the human subject's temporal lower cul-de-sac. Bio-sniffer devices for several kinds of gaseous substances, such as ethanol, trimethylamine, were developed using enzyme immobilized membrane and a reaction cell with both gas and liquid phase compartments separated by a porous diaphragm membrane.View full abstractDownload PDF (962K) -
Toru NAKURA, Shingo MANDAI, Makoto IKEDA, Kunihiro ASADAArticle type: Article
Session ID: IST2009-66
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper presents a Time Difference Amplifier (TDA) that amplifies the input time difference into the output time difference. Cross coupled chains of variable delay cells with the same number of stages are applicable for TDA, and the gain is adjusted via the closed-loop control. The TDA was fabricated using 65nm CMOS and the measurement results show that the time difference gain is 4.78 at a nominal power supply while the designed gain is 4.0. The gain is stable enough to be less than 1.4% gain shift under ±10% power supply voltage fluctuation.View full abstractDownload PDF (637K) -
Mhun Shin, Masayuki IKEBE, Junichi MOTOHISA, Eiichi SANOArticle type: Article
Session ID: IST2009-67
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe have proposed the method of re-measuring quantizing error of Single-Slope ADC for CMOS imager with TDC (Time-to-Digital Converter). Here, we examined adding TDC by D-FF with multi-phase clock, vis-a-vis Delay-line TDC with CMOS inverters. For the operation at 200MHz using 0.25um process, we verified to compensate the process variation of process within 8%, and to operate TDC in DNL: ±0.25LSB, INL: ±0.4LSB by simulation. In addition, utilizing deformation thermo-code, we reduced D-FFs of TDC. For 12bit A/D Converter, when the first stage 9bit ADC and the second stage 3bit TDC are considered, we can design the proposed ADC with only 13 of D-FFs. The linearity of A/D Converter due to the jitter of PLL or DLL and the process variation.View full abstractDownload PDF (1185K) -
Dong Ta Ngoc Huy, Masaya Miyahara, Akira MatsuzawaArticle type: Article
Session ID: IST2009-68
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSSwitch thermal noise represents a major limitation on the performance of switched-capacitor circuits. In these circuits, the total noise power can be reduced by increasing the sampling capacitance of the circuits. However, it also increases the settling time, hence requires high-performance opamps. This leads to larger power dissipation. A pole-zero cancellation method can be used to improve the settling time while maintaining the power consumption. This paper describes the noise effects caused by this settling time optimization technique in switched-capacitor amplifiers. Theory and simulation results show that the pole-zero cancellation is highly power-efficient technique, even though it increases the noise power.View full abstractDownload PDF (785K) -
Jun WANG, Toshimasa MATSUOKA, Kenji TANIGUCHIArticle type: Article
Session ID: IST2009-69
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper presents an inverter-based switched-capacitor integrator for 0.5V low-voltage applications. The proposed integrator utilizing floating voltage source and forward body bias obtains high performance as well as good independence of variations in process and temperature. It is applied to a 0.5V feedforward AD modulator. The test results indicate that the designed AD modulator achieves a peak SNDR of 71dB in a 78kHz bandwidth, and the core power consumption is only 860μW. This work is designed in a standard 0.18μm CMOS process.View full abstractDownload PDF (846K) -
Atsushi IWATAArticle type: Article
Session ID: IST2009-70
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSMany kinds of AD conversion schemes of Successive approximation, Flash, Pipelined, Delta Sigma, were proposed and integrated AD conversion devices with wide range of signal bandwidth: DC-10GHz and resolution: 3-20bits, have been developed. Currently ADCs become indispensable for all systems in information processing, communication, sensing, and control. AD conversion techniques have been developed with the progress of device scaling and digital systems. In the scaled CMOS era, development of high performance converters which have high efficiency in dissipation power and chip area, and be integrated to large scale logic chips, becomes the major subject. Recently, the traditional Successive Approximation AD conversion technique has been developed recursively, because the scheme is suitable to attain high speed combining with the time-domain interleave scheme, because of it features of low power dissipation and small size. To relax accuracy and noise of scaled devices, automatic digital error correction techniques, especially, background calibration which can eliminates variations due to process, voltage and temperature have also been intensively developed.View full abstractDownload PDF (1051K) -
Daehwa PAIK, Yusuke ASADA, Masaya MIYAHARA, Akira MATSUZAWAArticle type: Article
Session ID: IST2009-71
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper describes a flash ADC using interpolation (IP) and cyclic background self-calibrating techniques. The proposed IP technique that is cascade of capacitor IP and gate IP with dynamic double-tail latched comparator reduces non-linearity, power consumption, and occupied area. The cyclic background self-calibrating technique periodically suppresses offset mismatch voltages caused by static fluctuation and dynamic fluctuation due to temperature and supply voltage changes. The ADC has been fabricated in 90-nm 1P10M CMOS technology. Experimental results show that the ADC achieves ENOB of 6.07bits without calibration and 6.74bits with calibration up to 500MHz input signal at sampling rate of 600MSps. It dissipates 98.5mW on 1.2-V supply. FoM is 1.54pJ/conversion step.View full abstractDownload PDF (1052K) -
Koji Asami, Tsuyoshi Kurosawa, Takenori Tateiwa, Hiroyuki Miyajima, Ha ...Article type: Article
Session ID: IST2009-72
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper describes a new method to compensate for the timing skew effects in time-interleaved ADC systems. The proposed method uses our new linear phase digital filter whose group-delay can be set to an arbitrary value; the one of a conventional linear phase filter can be set to only the integer multiples of a half of its sampling period and hence the conventional filter cannot be applied to the skew effect correction. We describe our new linear phase digital filter and propose its design method for timing skew effect compensation. We have also performed simulation of applying our digital filters to timing skew correction in a time-interleaved ADC system and validated its effectiveness.View full abstractDownload PDF (679K) -
Yuji Nakajima, Akemi Sakaguchi, Toshio Ohkido, Tetsuya Matsumoto, Mich ...Article type: Article
Session ID: IST2009-73
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe have developed a 6b 2.7GS/s Folding ADC with on-chip self-background calibration in 90nm CMOS. This is the first report of a successful background-calibrated ADC with a sampling rate of multi GHz. The algorithm enabled us to realize a system robust against environmental and process variation. To minimize the power consumption, a cascaded-calibration architecture was developed. The ADC dissipates 50mW at 2.7GS/s from a 1.0V supply. The figure of merit is 0.47pJ/conversion-step, which is the best reported value for multi-GHz ADCs with a resolution of 6bit or more.View full abstractDownload PDF (1298K) -
Satoshi TanakaArticle type: Article
Session ID: IST2009-74
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper describes resent technology trend of mixed analog digital RF circuits. With progress of CMOS technology, large-scale digital signal processing and control function can be integrated in RF integrated circuit and some analog signal process blocks can be translated to digital signal processing units. In the same time, the design of remaining analog functional blocks becomes very hard.. The evolution of RF circuit technique in these 20 year is reviewed and some tradeoff between conventional analog circuit and digital RF circuit is discussed..View full abstractDownload PDF (817K) -
[in Japanese], [in Japanese], [in Japanese], [in Japanese], [in Japane ...Article type: Article
Session ID: IST2009-75
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESS -
Toru Masuda, Nobuhiro Shiramizu, Takahiro Nakamura, Katsuyoshi WashioArticle type: Article
Session ID: IST2009-76
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSAn image-rejection low-noise amplifier (LNA) based on 0.18-μm SiGe BiCMOS technology was developed in order to create a 24GHz-band RF receiver front-end. Its high image-rejection ratio (IRR) in the quasi-millimeter-wave frequency region is due to the use of a notch feedback circuit. The LNA has a 14-dB gain at an operating frequency of 27.2GHz and an IRR greater than 50dB IRR at an image frequency of 21.6GHz. While its IIP3 is -14dBm, its power consumption with a 1.2-V power supply is also low, 7.9mW.View full abstractDownload PDF (895K) -
Takatsugu KAMATA, Kazunori OKUI, Masahiko FUKASAWA, Kazuyoshi TANAKA, ...Article type: Article
Session ID: IST2009-77
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA zero-IF Tuner IC with wide RF input range (92dB) and low power consumption (528mW in a single 3.3V supply) for full-segment ISDB-T digital broadcast reception was realized using 0.25μm RF-CMOS technology. Instead of external SAW filters, 10-th order baseband filters were implemented. The wideband receiver selects one of two LNAs in condition of full-segment ISDB-T 64QAM modulation (CR=3/4), provides either low-IF or direct-IF and its sensitivity achieved -80dBm.View full abstractDownload PDF (938K) -
Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hyeokjong Lee, Tosh ...Article type: Article
Session ID: IST2009-78
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIn this paper, we propose a single-chip ultra low-power sensor node processor with a synchronous media access control (MAC). It is comprised of a transceiver, i8051 micro processor, and dedicated MAC processor. The test chip occupies 3x3mm^2 in a 180-nm CMOS process, including 1.38M transistors. The power is 58.0μW under a network environment.View full abstractDownload PDF (1033K) -
Mamoru SATO, Hiroyuki ABE, Tadahiro KURODA, Hiroki ISHIKUROArticle type: Article
Session ID: IST2009-79
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper reports a highly linear RF sampler with wide operating frequency range and power supply range. A clock bootstrapping circuit is proposed to decrease both the on-resistance and off-leakage of advanced MOSFETs while considering the device reliability. The proposed RF sampler circuit has been implemented in 90nm CMOS process, and excellent IIP3 has been obtained at wide frequency range up to 5GHz and 2GHz when the power supply is 1.2V and 0.5V, respectively.View full abstractDownload PDF (961K) -
Takahide TERADA, Koji NASU, Taizo YAMAWAKI, Masaru KOKUBOArticle type: Article
Session ID: IST2009-80
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA programmable Gm-C filter with digital calibration for hard disk drive read channels was developed. The filter has gm and boost tuning circuits and DC offset cancellation circuits. Moreover, it has two types of digital calibrations for achieving a robust filter response. One is an initial calibration to compensate for the filter response variations over process changes. The other is a periodic calibration to compensate for the variations over supply voltage and temperature changes. The periodic calibration operates in the duration between the servo and the data operation modes in the read channel. As a result, the filter response is robust over process, supply voltage, and temperature variations. The programmable range of the cutoff frequency and the boost are 100-1000MHz and 0-12dB, respectively.View full abstractDownload PDF (1033K) -
Ken UENO, Tetsuya ASAI, Yoshihito AMEMIYAArticle type: Article
Session ID: IST2009-81
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA temperature- and supply-independent clock generator has been developed using 0.35-μm CMOS technology. This generator is based on a simple frequency-locked loop technique and can be implemented monolithically without using LC resonant circuits, quartz resonators, and MEMS oscillators. A sample device that is tunable over a wide frequency range of 2-100MHz was designed and fabricated. It showed a temperature coefficient of 90ppm/℃, a line regulation of 4%/V, and a power dissipation of 180μW, at a frequency of 30MHz. The process sensitivity (σ/μ) was 2.7%. This clock generator can be used as an on-chip reference clock circuit.View full abstractDownload PDF (1035K) -
Yuji OSAKI, Tetsuya HIROSE, Kei MATSUMOTO, Nobutaka KUROKI, Masahiro N ...Article type: Article
Session ID: IST2009-82
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSSubthreshold LSIs can achieve ultra-low power. However, threshold voltage variations with temperature and fabrication process have significant impact on the circuit performance. In subthreshold digital circuits, delay time changes exponentially with threshold-voltage variations. To solve this problem, we propose a delay-compensation technique for subthreshold digital circuits. On-chip threshold-voltage monitoring and supply-voltage scaling are adopted to mitigate threshold-voltage variations. As examples of subthreshold digital circuits, we have evaluated the delay time in a ring oscillator and an 8-bit ripple carry adder. With the proposed techinque, the delay time can be improved from log-normal to normal distribution.View full abstractDownload PDF (930K) -
Article type: Appendix
Pages App1-
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (85K) -
Article type: Appendix
Pages App2-
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (85K) -
Article type: Appendix
Pages App3-
Published: October 01, 2009
Released on J-STAGE: September 20, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (85K)
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