Abstract
We have proposed the method of re-measuring quantizing error of Single-Slope ADC for CMOS imager with TDC (Time-to-Digital Converter). Here, we examined adding TDC by D-FF with multi-phase clock, vis-a-vis Delay-line TDC with CMOS inverters. For the operation at 200MHz using 0.25um process, we verified to compensate the process variation of process within 8%, and to operate TDC in DNL: ±0.25LSB, INL: ±0.4LSB by simulation. In addition, utilizing deformation thermo-code, we reduced D-FFs of TDC. For 12bit A/D Converter, when the first stage 9bit ADC and the second stage 3bit TDC are considered, we can design the proposed ADC with only 13 of D-FFs. The linearity of A/D Converter due to the jitter of PLL or DLL and the process variation.
