In order to reduce the data voltage of PDP, a drive technique utilizing a floating pulse was developed for a self-erase-discharge addressing. Floating pulse enables a use of higher wall-charge-accumulating pulse voltage, resulting in the reduction of address voltage. With the address technique, minimum address voltage was 0V. Light emission duty was 70% when the number of groups and subfields were 3 and 15, respectively. Voltage margin of the wall-charge-accumulation pulse was 10V.
