Column parallel SS-ADC with TDC using multi-phase clock signals for CMOS imagers(Circuit technologies,2nd Asian Image Sensors and Imaging Systems Symposium)

Abstract

We propose a single-slop ADC with a time to digital converter (TDC) that uses a multi-phase clock. When the TDC with resolution of n bits is adapted to the ADC, the conversion time is reduced by a factor of 2^n. Applying the TDC that uses multi-phase-clock signal reduced the number of circuit elements, achieved consistency between the single-slope ADC and the TDC, and realized robust meta-stability.