Abstract
Based on the 1.1um, 8M-pixel tsmc process development vehicle made with 45nm CIS technology, the source decomposition of Dark Fixed Pattern Noise (Dark FPN, DFPN) and its improvement are demonstrated along with the process optimization using Stacked CIS technology. Negative Transfer Gate Bias Operation (NB), Positive Transfer Gate Bias Operation (PB) and Floating Diffusion Leakage (FD) are three main sources, and the process optimization with Stacked CIS technology provides 20 percent total DFPN improvement with the significant reduction to PB and FD-DFPN. This result successfully demonstrates the possibility of the Stacked CIS for the pixel performance improvement, with pointing out the remaining room of improvement to NB-DFPN.