All issues
Predecessor
39.35
Displaying 1-19 of 19 articles from this issue
- |<
- <
- 1
- >
- >|
-
Article type: Cover
Pages Cover1-
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (11K) -
Article type: Index
Pages Toc1-
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (78K) -
Masahiro KOBAYASHI, Michiko JOHNSON, Yoichi WADA, Hiromasa TSUBOI, Hid ...Article type: Article
Session ID: IST2015-43
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIn this paper, we describe a device structure and optical design for a CMOS image sensor with the phase-difference detection photodiodes (PD) for an autofocus (AF) function. This image sensor has a pixel separated into two PDs by a PN junction. All the effective pixels function as both the imaging and the phase-difference detection AF (PDAF). We have realized a low dark random noise (=1.8e- at 1PD, 2.5e- at 1pixel) and high sensitivity (=78,000e-/lx・sec at 1green pixel) image sensor with the imaging and the PDAF functions in all the effective pixels.View full abstractDownload PDF (5485K) -
Atsushi Morimitsu, Isao Hirota, Sozo Yokogawa, Isao Ohdaira, Masao Mat ...Article type: Article
Session ID: IST2015-44
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe introduce a 1.58μm back illuminated CMOS image-sensor (BI CIS) which contains 4 Mega 2×1 shared on-chip micro-lenses (OCL). With this architecture, we realize a full phase-detection auto focus (PDAF) CIS, where all photo detectors (PDs) are L/R paired with a common OCL, the same color on-chip-color-filter (OCCF) and without metal grid between the L/R pixel boundary. The device has a good separation ratio of 2.59 and is more than twice sensitive under normal incident 550nm plane wave compared to current state-of-the-art PDAF pixels with half metal-shielded aperture. Because the device has no obstacle structure on its optical path, it hardly suffers from reflection and diffraction of the incident light. This feature is adequate to realize PDAF function especially for the CISs with smaller pixels. In addition, the OCCF configuration of the device is a 45° rotated to Bayer CF pattern, and hence, every 2 lines contain only Green pixels. This CF configuration makes it suitable to detect the phase difference between L and R sub-images. Furthermore, this architecture is in particular suitable for HDR imaging by varying the exposure times for each L and R sub-images because it is possible to capture two set of sub-images with almost identical optical characteristics to the on-focus object. In this paper, we report on the device performance and propose versatile applications including high-sensitive AF and HDR for the full-PDAF CIS.View full abstractDownload PDF (8536K) -
Toru Kondo, Yoshiaki Takemoto, Kenji Kobayashi, Mitsuhiro Tsukimura, N ...Article type: Article
Session ID: IST2015-45
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe have developed a 16Mpixel 3D stacked global-shutter CMOS image sensor with pixel level interconnections using 4 million micro bumps. The four photodiodes in the unit pixel circuit on the top substrate share one micro-bump interconnection in 7.6μm pitch. Each signal of the photodiodes is transferred to the corresponding storage node on the bottom substrate via the interconnection to achieve a global shutter function. The ratio of the parasitic light sensitivity of an in-pixel storage node and the light sensitivity of a photodiode is -180dB with 3.8μm pixel size.View full abstractDownload PDF (4816K) -
Yuichiro YAMASHITA, Wen-Hau WU, Wen-Jen CHIANG, Chi-Hsien CHUNG, Ren-J ...Article type: Article
Session ID: IST2015-46
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSBased on the 1.1um, 8M-pixel tsmc process development vehicle made with 45nm CIS technology, the source decomposition of Dark Fixed Pattern Noise (Dark FPN, DFPN) and its improvement are demonstrated along with the process optimization using Stacked CIS technology. Negative Transfer Gate Bias Operation (NB), Positive Transfer Gate Bias Operation (PB) and Floating Diffusion Leakage (FD) are three main sources, and the process optimization with Stacked CIS technology provides 20 percent total DFPN improvement with the significant reduction to PB and FD-DFPN. This result successfully demonstrates the possibility of the Stacked CIS for the pixel performance improvement, with pointing out the remaining room of improvement to NB-DFPN.View full abstractDownload PDF (438K) -
Masayuki IKEBE, Daisuke UCHIDA, Yasuhiro TAKE, Makito SOMEYA, Satoshi ...Article type: Article
Session ID: IST2015-47
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper proposes 3D stacked module consisting of image sensor and digital logic dies connected through inductive coupling channels. Evaluation of a prototype module revealed radiation noise from the inductive coils to the image sensor is less than 0.4-LSB range along with ADC code, i.e., negligible. Aiming at high frame rate image sensor/processing module exploiting this attractive off-die interface, we also worked on resolving another throughput-limiter, namely power consuming TDC used in column parallel ADCs. Novel intermittent TDC operation scheme presented in this paper can reduce its power dissipation 57% from conventional ones.View full abstractDownload PDF (13103K) -
Atsushi KOBAYASHIArticle type: Article
Session ID: IST2015-48
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSBasic performance of some image sensors might be lower than what we expect, because pixel size of image sensors for smart phones has been shrunk to 1.12um or smaller. We strongly expect that image sensors should be improved without sacrifice of characteristics-higher full well capacity, better quantum efficiency and lower noise.View full abstractDownload PDF (520K) -
Toshio YASUE, Kazuya KITAMURA, Toshihisa WATABE, Hiroshi SHIMAMOTO, To ...Article type: Article
Session ID: IST2015-49
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe fabricated a 33-Megapixel and 120-fps CMOS image sensor with 14-bit analog-to-digital converters (ADCs) using depletion-mode MOS (DMOS) capacitors. The DMOS capacitor has high capacitance density, whereas its capacitance depends on input voltage. Hence it has been not thought to be suitable for ADCs. We used two-stage cyclic ADC architecture with a split-sampling-capacitor method to reduce the differential non-linearity (DNL) of ADC. As a result, the fabricated image sensor exhibited a DNL of +0.95/-0.80 LSB, realizing genuine 14-bit resolution. Meanwhile, this image sensor exhibited a sensitivity of 3.57 V/lx-s by hiring nanofabricated 90 nm manufacturing process in analog circuit.View full abstractDownload PDF (5830K) -
Toshihisa WATABE, Kazuya KITAMURA, Tomohiko KOSUGI, Hiroshi OHTAKE, Hi ...Article type: Article
Session ID: IST2015-50
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe have been researching and developing a digital calibration technique for a two-stage single-ended cyclic ADC suitable for a 33-Mpixel 120-fps 8K Super High-Vision CMOS image sensor to improve the nonlinearity of the ADC. The technique needs to accurately determine error coefficients that define the quantity of errors caused in the ADC. However, the error coefficients have so far been determined on the basis of estimation from the design parameters of the ADC. Therefore, we proposed a new ADC operation and signal processing scheme to determine them accurately and dynamically by measuring the ADC output code including the errors and verified its effectiveness for precise and dynamic digital calibration by performing a preliminary experiment using the ADC test circuit.View full abstractDownload PDF (3461K) -
Yoshiyuki Kurokawa, Takashi Nakagawa, Shuhei Maeda, Takuro Ohmaru, Tak ...Article type: Article
Session ID: IST2015-51
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSTo realize a high-sensitivity CMOS image sensor using avalanche multiplication, we investigate the feasibility of a pixel structure that uses a crystalline selenium-based photoelectric conversion element and a crystalline oxide semiconductor (OS)-based FET. The OS FET is shown to have a withstand voltage of over 20 V, with which the photoelectric conversion element can cause avalanche multiplication. An amorphous selenium-based photoelectric conversion element in which holes are mainly travelling carriers and which is formed on a pixel electrode on a pseudo OS FET/CMOS FET substrate exhibits favorable photoconductivity, indicating compatibility with an OS FET/CMOS FET hybrid process. This shows the potential for realizing an OS/CMOS image sensor using avalanche multiplication in a crystalline selenium-based photoelectric conversion element.View full abstractDownload PDF (6697K) -
Hiroki KAMEHAMA, Sumeet SHRESTHA, Keita YASUTOMI, Keiichiro KAGAWA, Ay ...Article type: Article
Session ID: IST2015-52
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA novel SOI (Silicon-On-Insulator) pixel photo detector with full depletion and backgate surface potential pinning is proposed in this presentation. The detector greatly increases charge-to-voltage conversion gain while stabilizing the operation of SOI circuits. Low noise and wide dynamic range operations are attained. A double doping technique increasing potential barrier to holes at the surface region is effective for a stable operation to the variation of back bias voltage. The structure of the pixel detector, simulation results of potential distributions and measurement results are reported.View full abstractDownload PDF (4182K) -
V. T. S. Dao, Q. A. Nguyen, K. Kitagawa, K. Shimonomura, T. Etoh, N. M ...Article type: Article
Session ID: IST2015-53
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSFactors limiting the frame rate of the BSI MCG image senor proposed by the authors are listed, and the effect of each factor is analyzed. Based on the result, an image sensor structure to achieve the highest frame rate is proposed, and the practical and achievable highest frame rate is estimated. If we design the sensor with a design rule for a 130 nm CMOS/CCD hybrid process, the highest temporal resolution is about 180 ps. By employing a finer design rule, a higher temporal resolution of 100 ps, i.e., the highest frame rate of 10 Gfps can be achieved.View full abstractDownload PDF (671K) -
Masatoshi KIMURA, Tadashi YAMAGUCHI, Takashi KUROIArticle type: Article
Session ID: IST2015-54
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe propose a novel annealing technique in order to improve the dark characteristics for CMOS image sensor without deteriorating the transistor characteristics. Microwave annealing (MWA) has been studied as an alternative annealing technique for diffusion-less dopant activation and implantation damage recovery in advanced CMOS technology. We employed MWA technique in order to recover crystalline defects in CMOS image sensor (CIS) process. We demonstrate that MWA can be implemented a low thermal budget to obtain the effect of repairing the ion-implantation damage equivalent to conventional furnace annealing (FA). MWA can repair the process damage without transistor performance degradation.View full abstractDownload PDF (6645K) -
Satoshi NASUNO, Shunichi WAKASHIMA, Fumiaki KUSUHARA, Rihito KURODA, S ...Article type: Article
Session ID: IST2015-55
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIn this paper, a CMOS image sensor introducing wide spectral sensitive PD technology, small floating diffusion (FD) capacitance technology, lateral overflow integration capacitor (LOFIC) technology and buried channel technology is designed, fabricated and evaluated. A 5.6μm pixel pitch CMOS image sensor was fabricated using a 0.18μm 1P5M CMOS process technology. It achieved a high conversion gain (CG) of 240μV/e^-, a high full well capacity of 200ke^-, a wide spectral response for 190-1000 nm and a high robustness to deuterium lamp used as a UV light.View full abstractDownload PDF (5033K) -
Fumiaki KUSUHARA, Shunichi WAKASHIMA, Satoshi NASUNO, Rihito KURODA, S ...Article type: Article
Session ID: IST2015-56
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper reports the analysis and reduction technology of components of floating diffusion (FD) capacitance (C_<FD>) and its application to a high sensitivity and high full well capacity CMOS image sensor. We analyzed the result of C_<FD> components extracted by the developed test patterns, and proposed FD structure with non-LDD and low concentration diffusion layer to reduce C_<FD>. CMOS image sensor which has 360^H×1680^V pixels fabricated by 0.18μm CMOS process technology with lateral overflow integration capacitor (LOFIC), dual gain column amplifier, floating capacitor load readout operation, buried channel pixel source follower (SF) transistor and low C_<FD> device structure was evaluated and it exhibited 243 μV/e^- of conversion gain (CG), 0.46e^-_<rms> of readout noise, and 76ke^- of full well capacity (FWC).View full abstractDownload PDF (5556K) -
Article type: Appendix
Pages App1-
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (81K) -
Article type: Appendix
Pages App2-
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (81K) -
Article type: Appendix
Pages App3-
Published: September 11, 2015
Released on J-STAGE: September 22, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (81K)
- |<
- <
- 1
- >
- >|