2nd Order Delta-Sigma ADC using Voltage Controlled Ring-Delay Line

Abstract

We propose a 2nd-order delta-sigma ADC using a TAD :Time Analog to Digital converter as 1st stage. The TAD consists of a voltage-controlled ring-delay line with even number of CMOS inverters for lower-bits output and a counter for upper-bits one; it realizes all-digital ADC configuration. When a digital integrator is used for first stage of higher-order delta-sigma modulation, 1st-order noise-shaping characteristic dominates quantization noise components. However, using TAD for the 1st stage, 2nd-order noise-shaping characteristic can be realized. We also confirmed the noise characteristics by numerical simulation. This results leads realization of fully-digital 2nd-order delta-sigma ADC.