FPGAへの暗号回路実装方法の検討と電力差分解析に対する耐性評価

浅井 稔也; 吉川 雅弥

doi:10.11511/jacc.53.0.110.0

THE 53RD JAPAN JOINT AUTOMATIC CONTROL CONFERENCE

Session ID : 278

DOI https://doi.org/10.11511/jacc.53.0.110.0

Conference information

Host: The Japan Society of Mechanical Engineers, The Society of Instrument and Control Engineers, The Institute of Systems, Control and Information Engineers, The Society of Chemical Engineers, Japan, The Japan Society for Precision Engineering, The Japan Society for Aeronautical and Space Sciences

Co-host: Technically Cosponsored by 50 Societies and Institutes

Measuring Technology 2

FPGA implementation for cryptographic device and it's evaluation of DPA-Registant

*Toshiya Asai, Masaya Yoshikawa

Author information

Keywords: Differential power analysis, FPGA, Implementation technique, cryptographic device

CONFERENCE PROCEEDINGS FREE ACCESS

Details

Abstract

Differential power analysis (DPA) is one of the side-channel attacks in which analysis is statistically performed focusing on power consumption. The DPA utilizes the correlation between a specific bit and power consumption during cipher processing. In this paper, we propose a new FPGA implementation technique for DPA, and experimental results show the validity of the proposed technique.

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